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ST72321AR6 Datasheet

  • ST72321AR6

  • 8-BIT MCU WITH NESTED INTERRUPTS, FLASH,10-BIT ADC, FIVE TIM...

  • STMicroelectronics   STMicroelectronics

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ST72321
SERIAL PERIPHERAL INTERFACE
(Cont鈥檇)
CONTROL/STATUS REGISTER (SPICSR)
Read/Write (some bits Read Only)
Reset Value: 0000 0000 (00h)
7
SPIF
WCOL
OVR
MODF
-
SOD
SSM
0
SSI
Bit 3 = Reserved, must be kept cleared.
Bit 2 =
SOD
SPI Output Disable.
This bit is set and cleared by software. When set, it
disables the alternate function of the SPI output
(MOSI in master mode / MISO in slave mode)
0: SPI output enabled (if SPE=1)
1: SPI output disabled
Bit 1 =
SSM
SS Management.
This bit is set and cleared by software. When set, it
disables the alternate function of the SPI SS pin
and uses the SSI bit value instead. See
Section
10.5.3.2 Slave Select Management.
0: Hardware management (SS managed by exter-
nal pin)
1: Software management (internal SS signal con-
trolled by SSI bit. External SS pin free for gener-
al-purpose I/O)
Bit 0 =
SSI
SS Internal Mode.
This bit is set and cleared by software. It acts as a
鈥榗hip select鈥?by controlling the level of the SS slave
select signal when the SSM bit is set.
0 : Slave selected
1 : Slave deselected
DATA I/O REGISTER (SPIDR)
Read/Write
Reset Value: Undefined
7
0
D6
D5
D4
D3
D2
D1
D0
Bit 7 =
SPIF
Serial Peripheral Data Transfer Flag
(Read only).
This bit is set by hardware when a transfer has
been completed. An interrupt is generated if
SPIE=1 in the SPICR register. It is cleared by a
software sequence (an access to the SPICSR
register followed by a write or a read to the
SPIDR register).
0: Data transfer is in progress or the flag has been
cleared.
1: Data transfer between the device and an exter-
nal device has been completed.
Note:
While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR reg-
ister is read.
Bit 6 =
WCOL
Write Collision status (Read only).
This bit is set by hardware when a write to the
SPIDR register is done during a transmit se-
quence. It is cleared by a software sequence (see
Figure 58).
0: No write collision occurred
1: A write collision has been detected
Bit 5 =
OVR
SPI
Overrun error (Read only).
This bit is set by hardware when the byte currently
being received in the shift register is ready to be
transferred into the SPIDR register while SPIF = 1
(See
Section 10.5.5.2).
An interrupt is generated if
SPIE = 1 in SPICSR register. The OVR bit is
cleared by software reading the SPICSR register.
0: No overrun error
1: Overrun error detected
Bit 4 =
MODF
Mode Fault flag (Read only).
This bit is set by hardware when the SS pin is
pulled low in master mode (see
Section 10.5.5.1
Master Mode Fault (MODF)).
An SPI interrupt can
be generated if SPIE=1 in the SPICSR register.
This bit is cleared by a software sequence (An ac-
cess to the SPICSR register while MODF=1 fol-
lowed by a write to the SPICR register).
0: No master mode fault detected
1: A fault in master mode has been detected
D7
The SPIDR register is used to transmit and receive
data on the serial bus. In a master device, a write
to this register will initiate transmission/reception
of another byte.
Notes:
During the last clock cycle the SPIF bit is
set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads
the serial peripheral data I/O register, the buffer is
actually being read.
While the SPIF bit is set, all writes to the SPIDR
register are inhibited until the SPICSR register is
read.
Warning:
A write to the SPIDR register places
data directly into the shift register for transmission.
A read to the SPIDR register returns the value lo-
cated in the buffer and not the content of the shift
register (see
Figure 53).
97/185

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