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ST72321AR6 Datasheet

  • ST72321AR6

  • 8-BIT MCU WITH NESTED INTERRUPTS, FLASH,10-BIT ADC, FIVE TIM...

  • STMicroelectronics   STMicroelectronics

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ST72321
SERIAL PERIPHERAL INTERFACE
(Cont鈥檇)
10.5.6 Low Power Modes
Mode
WAIT
Description
No effect on SPI.
SPI interrupt events cause the device to exit
from WAIT mode.
SPI registers are frozen.
In HALT mode, the SPI is inactive. SPI oper-
ation resumes when the MCU is woken up by
an interrupt with 鈥渆xit from HALT mode鈥?ca-
pability. The data received is subsequently
read from the SPIDR register when the soft-
ware is running (interrupt vector fetching). If
several data are received before the wake-
up event, then an overrun error is generated.
This error can be detected after the fetch of
the interrupt routine that woke up the device.
SPI exits from Slave mode, it returns to normal
state immediately.
Caution:
The SPI can wake up the ST7 from Halt
mode only if the Slave Select signal (external SS
pin or the SSI bit in the SPICSR register) is low
when the ST7 enters Halt mode. So if Slave selec-
tion is configured as external (see
Section
10.5.3.2),
make sure the master drives a low level
on the SS pin when the slave enters Halt mode.
10.5.7 Interrupts
Interrupt Event
SPI End of Transfer
Event
Master Mode Fault
Event
Overrun Error
Event
Flag
SPIF
MODF
OVR
SPIE
Enable
Control
Bit
Exit
from
Wait
Yes
Yes
Yes
Exit
from
Halt
Yes
No
No
HALT
10.5.6.1 Using the SPI to wakeup the MCU from
Halt mode
In slave configuration, the SPI is able to wakeup
the ST7 device from HALT mode through a SPIF
interrupt. The data received is subsequently read
from the SPIDR register when the software is run-
ning (interrupt vector fetch). If multiple data trans-
fers have been performed before software clears
the SPIF bit, then the OVR bit is set by hardware.
Note:
When waking up from Halt mode, if the SPI
remains in Slave mode, it is recommended to per-
form an extra communications cycle to bring the
SPI from Halt mode state to normal state. If the
Note:
The SPI interrupt events are connected to
the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the interrupt mask in
the CC register is reset (RIM instruction).
95/185

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