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ST72321AR6 Datasheet

  • ST72321AR6

  • 8-BIT MCU WITH NESTED INTERRUPTS, FLASH,10-BIT ADC, FIVE TIM...

  • STMicroelectronics   STMicroelectronics

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ST72321
SERIAL PERIPHERAL INTERFACE
(Cont鈥檇)
10.5.4 Clock Phase and Clock Polarity
Four possible timing relationships may be chosen
by software, using the CPOL and CPHA bits (See
Figure 57).
Note:
The idle state of SCK must correspond to
the polarity selected in the SPICSR register (by
pulling up SCK if CPOL=1 or pulling down SCK if
CPOL=0).
The combination of the CPOL clock polarity and
CPHA (clock phase) bits selects the data capture
clock edge
Figure 57. Data Clock Timing Diagram
Figure 57,
shows an SPI transfer with the four
combinations of the CPHA and CPOL bits. The di-
agram may be interpreted as a master or slave
timing diagram where the SCK pin, the MISO pin,
the MOSI pin are directly connected between the
master and the slave device.
Note:
If CPOL is changed at the communication
byte boundaries, the SPI must be disabled by re-
setting the SPE bit.
CPHA =1
SCK
(CPOL = 1)
SCK
(CPOL = 0)
MISO
(from master)
MOSI
(from slave)
SS
(to slave)
CAPTURE STROBE
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
CPHA =0
SCK
(CPOL = 1)
SCK
(CPOL = 0)
MISO
(from master)
MOSI
(from slave)
SS
(to slave)
CAPTURE STROBE
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
Note:
This figure should not be used as a replacement for parametric information.
Refer to the Electrical Characteristics chapter.
92/185

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