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ST72321AR6 Datasheet

  • ST72321AR6

  • 8-BIT MCU WITH NESTED INTERRUPTS, FLASH,10-BIT ADC, FIVE TIM...

  • STMicroelectronics   STMicroelectronics

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ST72321
SERIAL PERIPHERAL INTERFACE
(Cont鈥檇)
10.5.3.2 Slave Select Management
As an alternative to using the SS pin to control the
Slave Select signal, the application can choose to
manage the Slave Select signal by software. This
is configured by the SSM bit in the SPICSR regis-
ter (see
Figure 56)
In software management, the external SS pin is
free for other application uses and the internal SS
signal level is driven by writing to the SSI bit in the
SPICSR register.
In Master mode:
鈥?SS internal must be held high continuously
In Slave Mode:
There are two cases depending on the data/clock
timing relationship (see
Figure 55):
If CPHA=1 (data latched on 2nd clock edge):
鈥?SS internal must be held low during the entire
transmission. This implies that in single slave
applications the SS pin either can be tied to
V
SS
, or made free for standard I/O by manag-
ing the SS function by software (SSM= 1 and
SSI=0 in the in the SPICSR register)
If CPHA=0 (data latched on 1st clock edge):
鈥?SS internal must be held low during byte
transmission and pulled high between each
byte to allow the slave to write to the shift reg-
ister. If SS is not pulled high, a Write Collision
error will occur when the slave writes to the
shift register (see
Section 10.5.5.3).
Figure 55. Generic SS Timing Diagram
MOSI/MISO
Master SS
Slave SS
(if CPHA=0)
Slave SS
(if CPHA=1)
Byte 1
Byte 2
Byte 3
Figure 56. Hardware/Software Slave Select Management
SSM bit
SSI bit
SS external pin
1
0
SS internal
90/185

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