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ST72321AR6 Datasheet

  • ST72321AR6

  • 8-BIT MCU WITH NESTED INTERRUPTS, FLASH,10-BIT ADC, FIVE TIM...

  • STMicroelectronics   STMicroelectronics

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ST72321
10.5 SERIAL PERIPHERAL INTERFACE (SPI)
10.5.1 Introduction
The Serial Peripheral Interface (SPI) allows full-
duplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master and one or more slaves however the SPI
interface can not be a master in a multi-master
system.
10.5.2 Main Features
s
Full duplex synchronous transfers (on 3 lines)
s
Simplex synchronous transfers (on 2 lines)
s
Master or slave operation
s
Six master mode frequencies (f
CPU
/4 max.)
s
f
CPU
/2 max. slave mode frequency
s
SS Management by software or hardware
s
Programmable clock polarity and phase
s
End of transfer interrupt flag
s
Write collision, Master Mode Fault and Overrun
flags
10.5.3 General Description
Figure 53
shows the serial peripheral interface
(SPI) block diagram. There are 3 registers:
鈥?SPI Control Register (SPICR)
鈥?SPI Control/Status Register (SPICSR)
鈥?SPI Data Register (SPIDR)
The SPI is connected to external devices through
3 pins:
鈥?MISO: Master In / Slave Out data
鈥?MOSI: Master Out / Slave In data
鈥?SCK: Serial Clock out by SPI masters and in-
put by SPI slaves
鈥?SS: Slave select:
This input signal acts as a 鈥榗hip select鈥?to let
the SPI master communicate with slaves indi-
vidually and to avoid contention on the data
lines. Slave SS inputs can be driven by stand-
ard I/O ports on the master MCU.
Figure 53. Serial Peripheral Interface Block Diagram
Data/Address Bus
SPIDR
Read
Read Buffer
Interrupt
request
MOSI
MISO
8-Bit Shift Register
7
SPIF WCOL OVR MODF
0
SPICSR
SOD SSM
0
SSI
SOD
bit
Write
SS
SPI
STATE
CONTROL
7
SPIE
1
0
SCK
SPICR
0
SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
MASTER
CONTROL
SERIAL CLOCK
GENERATOR
SS
88/185

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