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ST72321AR6 Datasheet

  • ST72321AR6

  • 8-BIT MCU WITH NESTED INTERRUPTS, FLASH,10-BIT ADC, FIVE TIM...

  • STMicroelectronics   STMicroelectronics

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ST72321
16-BIT TIMER
(Cont鈥檇)
10.4.3.4 Output Compare
In this section, the index,
i,
may be 1 or 2 because
there are 2 output compare functions in the 16-bit
timer.
This function can be used to control an output
waveform or indicate when a period of time has
elapsed.
When a match is found between the Output Com-
pare register and the free running counter, the out-
put compare function:
鈥?Assigns pins with a programmable value if the
OCiE bit is set
鈥?Sets a flag in the status register
鈥?Generates an interrupt if enabled
Two 16-bit registers Output Compare Register 1
(OC1R) and Output Compare Register 2 (OC2R)
contain the value to be compared to the counter
register each timer clock cycle.
OCiR
MS Byte
OCiHR
LS Byte
OCiLR
鈥?The OCMPi pin takes OLVLi bit value (OCMPi
pin latch is forced low during reset).
鈥?A timer interrupt is generated if the OCIE bit is
set in the CR1 register and the I bit is cleared in
the CC register (CC).
The OC
i
R register value required for a specific tim-
ing application can be calculated using the follow-
ing formula:
鈭?/div>
OCiR =
鈭唗
*
f
CPU
PRESC
Where:
鈭?/div>
t
= Output compare period (in seconds)
= CPU clock frequency (in hertz)
f
CPU
PRESC
= Timer prescaler factor (2, 4 or 8 de-
pending on CC[1:0] bits, see
Table 16
Clock Control Bits)
If the timer clock is an external clock, the formula
is:
These registers are readable and writable and are
not affected by the timer hardware. A reset event
changes the OC
i
R value to 8000h.
Timing resolution is one count of the free running
counter: (
f
CPU/
CC[1:0]
).
Procedure:
To use the output compare function, select the fol-
lowing in the CR2 register:
鈥?Set the OCiE bit if an output is needed then the
OCMPi pin is dedicated to the output compare
i
signal.
鈥?Select the timer clock (CC[1:0]) (see
Table 16
Clock Control Bits).
And select the following in the CR1 register:
鈥?Select the OLVLi bit to applied to the OCMP
i
pins
after the match occurs.
鈥?Set the OCIE bit to generate an interrupt if it is
needed.
When a match is found between OCRi register
and CR register:
鈥?OCFi bit is set.
鈭?/div>
OCiR =
鈭唗
*
f
EXT
Where:
鈭?/div>
t
= Output compare period (in seconds)
= External timer clock frequency (in hertz)
f
EXT
Clearing the output compare interrupt request (i.e.
clearing the OCFi bit) is done by:
1. Reading the SR register while the OCFi bit is
set.
2. An access (read or write) to the OCiLR register.
The following procedure is recommended to pre-
vent the OCFi bit from being set between the time
it is read and the write to the OC
i
R register:
鈥?Write to the OCiHR register (further compares
are inhibited).
鈥?Read the SR register (first step of the clearance
of the OCFi bit, which may be already set).
鈥?Write to the OCiLR register (enables the output
compare function and clears the OCFi bit).
75/185

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