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ST72321AR6 Datasheet

  • ST72321AR6

  • 8-BIT MCU WITH NESTED INTERRUPTS, FLASH,10-BIT ADC, FIVE TIM...

  • STMicroelectronics   STMicroelectronics

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ST72321
PWM AUTO-RELOAD TIMER
(Cont鈥檇)
10.3.2 Functional Description
Counter
The free running 8-bit counter is fed by the output
of the prescaler, and is incremented on every ris-
ing edge of the clock signal.
It is possible to read or write the contents of the
counter on the fly by reading or writing the Counter
Access register (ARTCAR).
When a counter overflow occurs, the counter is
automatically reloaded with the contents of the
ARTARR register (the prescaler is not affected).
Counter clock and prescaler
The counter clock frequency is given by:
f
COUNTER
= f
INPUT
/ 2
CC[2:0]
The timer counter鈥檚 input clock (f
INPUT
) feeds the
7-bit programmable prescaler, which selects one
of the 8 available taps of the prescaler, as defined
by CC[2:0] bits in the Control/Status Register
(ARTCSR). Thus the division factor of the prescal-
er can be set to 2
n
(where n = 0, 1,..7).
This f
INPUT
frequency source is selected through
the EXCL bit of the ARTCSR register and can be
either the f
CPU
or an external input frequency f
EXT
.
The clock input to the counter is enabled by the
TCE (Timer Counter Enable) bit in the ARTCSR
register. When TCE is reset, the counter is
stopped and the prescaler and counter contents
are frozen. When TCE is set, the counter runs at
the rate of the selected clock source.
Figure 37. Output compare control
Counter and Prescaler Initialization
After RESET, the counter and the prescaler are
cleared and f
INPUT
= f
CPU
.
The counter can be initialized by:
鈥?Writing to the ARTARR register and then setting
the FCRL (Force Counter Re-Load) and the TCE
(Timer Counter Enable) bits in the ARTCSR reg-
ister.
鈥?Writing to the ARTCAR counter access register,
In both cases the 7-bit prescaler is also cleared,
whereupon counting will start from a known value.
Direct access to the prescaler is not possible.
Output compare control
The timer compare function is based on four differ-
ent comparisons with the counter (one for each
PWMx output). Each comparison is made be-
tween the counter value and an output compare
register (OCRx) value. This OCRx register can not
be accessed directly, it is loaded from the duty cy-
cle register (PWMDCRx) at each overflow of the
counter.
This double buffering method avoids glitch gener-
ation when changing the duty cycle on the fly.
f
COUNTER
ARTARR=FDh
COUNTER
FDh
FEh
FFh
FDh
FEh
FFh
FDh
FEh
FFh
OCRx
FDh
FEh
PWMDCRx
FDh
FEh
PWMx
61/185

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