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ST72321AR6 Datasheet

  • ST72321AR6

  • 8-BIT MCU WITH NESTED INTERRUPTS, FLASH,10-BIT ADC, FIVE TIM...

  • STMicroelectronics   STMicroelectronics

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ST72321
MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK
(Cont鈥檇)
Bit 0 =
OIF
Oscillator interrupt flag
This bit is set by hardware and cleared by software
reading the MCCSR register. It indicates when set
that the main oscillator has reached the selected
elapsed time (TB1:0).
0: Timeout not reached
1: Timeout reached
CAUTION:
The BRES and BSET instructions
must not be used on the MCCSR register to avoid
unintentionally clearing the OIF bit.
MCC BEEP CONTROL REGISTER (MCCBCR)
Read /Write
Reset Value: 0000 0000 (00h)
7
0
0
0
0
0
0
BC1
0
BC0
Bit 7:2 = Reserved, must be kept cleared.
Bit 1:0 =
BC[1:0]
Beep control
These 2 bits select the PF1 pin beep capability.
BC1
0
0
1
1
BC0
0
1
0
1
~2-KHz
~1-KHz
~500-Hz
Beep mode with f
OSC2
=8MHz
Off
Output
Beep signal
~50% duty cycle
The beep output signal is available in ACTIVE-
HALT mode but has to be disabled to reduce the
consumption.
Table 14. Main Clock Controller Register Map and Reset Values
Address
(Hex.)
002Bh
002Ch
002Dh
Register
Label
SICSR
Reset Value
MCCSR
Reset Value
MCCBCR
Reset Value
7
AVDS
0
MCO
0
0
6
AVDIE
0
CP1
0
0
5
AVDF
0
CP0
0
0
4
LVDRF
x
SMS
0
0
3
2
CSSIE
0
TB0
0
0
1
CSSD
0
OIE
0
BC1
0
0
WDGRF
x
OIF
0
BC0
0
0
TB1
0
0
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