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ST72321AR6 Datasheet

  • ST72321AR6

  • 8-BIT MCU WITH NESTED INTERRUPTS, FLASH,10-BIT ADC, FIVE TIM...

  • STMicroelectronics   STMicroelectronics

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ST72321
MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK
(Cont鈥檇)
10.2.5 Low Power Modes
Mode
WAIT
Description
No effect on MCC/RTC peripheral.
MCC/RTC interrupt cause the device to exit
from WAIT mode.
No effect on MCC/RTC counter (OIE bit is
set), the registers are frozen.
MCC/RTC interrupt cause the device to exit
from ACTIVE-HALT mode.
MCC/RTC counter and registers are frozen.
MCC/RTC operation resumes when the
MCU is woken up by an interrupt with 鈥渆xit
from HALT鈥?capability.
Bit 6:5 =
CP[1:0]
CPU clock prescaler
These bits select the CPU clock prescaler which is
applied in the different slow modes. Their action is
conditioned by the setting of the SMS bit. These
two bits are set and cleared by software
f
CPU
in SLOW mode
f
OSC2
/ 2
f
OSC2
/ 4
f
OSC2
/ 8
f
OSC2
/ 16
CP1
0
0
1
1
CP0
0
1
0
1
ACTIVE-
HALT
HALT
10.2.6 Interrupts
The MCC/RTC interrupt event generates an inter-
rupt if the OIE bit of the MCCSR register is set and
the interrupt mask in the CC register is not active
(RIM instruction).
Interrupt Event
Time base overflow
event
Enable
Event
Control
Flag
Bit
OIF
OIE
Exit
from
Wait
Yes
Exit
from
Halt
No
1)
Bit 4 =
SMS
Slow mode select
This bit is set and cleared by software.
0: Normal mode. f
CPU
=
f
OSC2
1: Slow mode. f
CPU
is given by CP1, CP0
See
Section 8.2 SLOW MODE
and
Section 10.2
MAIN CLOCK CONTROLLER WITH REAL TIME
CLOCK AND BEEPER (MCC/RTC)
for more de-
tails.
Bit 3:2 =
TB[1:0]
Time base control
These bits select the programmable divider time
base. They are set and cleared by software.
Time Base
Counter
Prescaler f
OSC2
=4MHz f
OSC2
=8MHz
16000
4ms
8ms
20ms
50ms
2ms
4ms
10ms
25ms
32000
80000
200000
TB1
0
0
1
1
TB0
0
1
0
1
Note:
The MCC/RTC interrupt wakes up the MCU from
ACTIVE-HALT mode, not from HALT mode.
10.2.7 Register Description
MCC CONTROL/STATUS REGISTER (MCCSR)
Read /Write
Reset Value: 0000 0000 (00h
)
7
MCO
CP1
CP0
SMS
TB1
TB0
OIE
0
OIF
A modification of the time base is taken into ac-
count at the end of the current period (previously
set) to avoid an unwanted time shift. This allows to
use this time base as a real time clock.
Bit 1 =
OIE
Oscillator interrupt enable
This bit set and cleared by software.
0: Oscillator interrupt disabled
1: Oscillator interrupt enabled
This interrupt can be used to exit from ACTIVE-
HALT mode.
When this bit is set, calling the ST7 software HALT
instruction enters the ACTIVE-HALT power saving
mode
.
Bit 7 =
MCO
Main clock out selection
This bit enables the MCO alternate function on the
PF0 I/O port. It is set and cleared by software.
0: MCO alternate function disabled (I/O pin free for
general-purpose I/O)
1: MCO alternate function enabled (f
CPU
on I/O
port)
Note:
To reduce power consumption, the MCO
function is not active in ACTIVE-HALT mode.
58/185

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