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ST72321AR6 Datasheet

  • ST72321AR6

  • 8-BIT MCU WITH NESTED INTERRUPTS, FLASH,10-BIT ADC, FIVE TIM...

  • STMicroelectronics   STMicroelectronics

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ST72321
POWER SAVING MODES
(Cont鈥檇)
8.4.2 HALT MODE
The HALT mode is the lowest power consumption
mode of the MCU. It is entered by executing the
鈥楬ALT鈥?instruction when the OIE bit of the Main
Clock Controller Status register (MCCSR) is
cleared (see
Section 10.2 on page 57
for more de-
tails on the MCCSR register).
The MCU can exit HALT mode on reception of ei-
ther a specific interrupt (see
Table 7, 鈥淚nterrupt
Mapping,鈥?on page 37)
or a RESET. When exiting
HALT mode by means of a RESET or an interrupt,
the oscillator is immediately turned on and the 256
or 4096 CPU cycle delay is used to stabilize the
oscillator. After the start up delay, the CPU
resumes operation by servicing the interrupt or by
fetching the reset vector which woke it up (see
Fig-
ure 29).
When entering HALT mode, the I[1:0] bits in the
CC register are forced to 鈥?0b鈥檛o enable interrupts.
Therefore, if an interrupt is pending, the MCU
wakes up immediately.
In HALT mode, the main oscillator is turned off
causing all internal processing to be stopped, in-
cluding the operation of the on-chip peripherals.
All peripherals are not clocked except the ones
which get their clock supply from another clock
generator (such as an external or auxiliary oscilla-
tor).
The compatibility of Watchdog operation with
HALT mode is configured by the 鈥淲DGHALT鈥?op-
tion bit of the option byte. The HALT instruction
when executed while the Watchdog system is en-
abled, can generate a Watchdog RESET (see
Section 14.1 on page 172
for more details).
Figure 28. HALT Timing Overview
RUN
HALT
256 OR 4096 CPU
CYCLE DELAY
RESET
OR
INTERRUPT
FETCH
VECTOR
FETCH RESET VECTOR
OR SERVICE INTERRUPT
RUN
Figure 29. HALT Mode Flow-chart
HALT
INSTRUCTION
(MCCSR.OIE=0)
ENABLE
WDGHALT
1)
1
WATCHDOG
RESET
OSCILLATOR
OFF
PERIPHERALS
2)
OFF
CPU
OFF
I[1:0] BITS
10
0
WATCHDOG
DISABLE
N
RESET
N
INTERRUPT
Y
Y
3)
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
ON
OFF
ON
XX
4)
256 OR 4096 CPU CLOCK
CYCLE DELAY
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
ON
ON
ON
XX
4)
HALT
INSTRUCTION
[MCCSR.OIE=0]
Notes:
1. WDGHALT is an option bit. See option byte sec-
tion for more details.
2. Peripheral clocked with an external clock source
can still be active.
3. Only some specific interrupts can exit the MCU
from HALT mode (such as external interrupt). Re-
fer to
Table 7, 鈥淚nterrupt Mapping,鈥?on page 37
for
more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
ister are set to the current software priority level of
the interrupt routine and recovered when the CC
register is popped.
44/185

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