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ST72321AR6 Datasheet

  • ST72321AR6

  • 8-BIT MCU WITH NESTED INTERRUPTS, FLASH,10-BIT ADC, FIVE TIM...

  • STMicroelectronics   STMicroelectronics

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ST72321
INTERRUPTS
(Cont鈥檇)
Table 7. Interrupt Mapping
N擄
Source
Block
RESET
TRAP
0
1
2
3
4
5
6
7
8
9
10
11
12
13
SPI
TIMER A
TIMER B
SCI
AVD
I2C
PWM ART
TLI
MCC/RTC
CSS
ei0
ei1
ei2
ei3
Reset
Software interrupt
External top level interrupt
Main clock controller time base interrupt
Safe oscillator activation interrupt
External interrupt port A3..0
External interrupt port F2..0
External interrupt port B3..0
External interrupt port B7..4
Not used
SPI peripheral interrupts
TIMER A peripheral interrupts
TIMER B peripheral interrupts
SCI Peripheral interrupts
Auxiliary Voltage detector interrupt
I2C Peripheral interrupts
PWM ART interrupt
SPICSR
TASR
TBSR
SCISR
SICSR
(see periph)
ARTCSR
Lower
Priority
yes
2
no
no
no
no
no
yes
3
N/A
Description
Register
Label
N/A
EICR
MCCSR
SICSR
Higher
Priority
Priority
Order
Exit
from
HALT
1)
yes
no
yes
yes
yes
yes
yes
yes
Address
Vector
FFFEh-FFFFh
FFFCh-FFFDh
FFFAh-FFFBh
FFF8h-FFF9h
FFF6h-FFF7h
FFF4h-FFF5h
FFF2h-FFF3h
FFF0h-FFF1h
FFEEh-FFEFh
FFECh-FFEDh
FFEAh-FFEBh
FFE8h-FFE9h
FFE6h-FFE7h
FFE4h-FFE5h
FFE2h-FFE3h
FFE0h-FFE1h
Notes:
1. Valid for HALT mode except for the MCC/RTC or CSS interrupt source which exits from ACTIVE-HALT
mode.
2. Exit from HALT possible when SPI is in slave mode.
3. Exit from HALT possible when PWM ART is in external clock mode.
7.6 EXTERNAL INTERRUPTS
7.6.1 I/O Port Interrupt Sensitivity
The external interrupt sensitivity is controlled by
the IPA, IPB and ISxx bits of the EICR register
(Figure
22).
This control allows to have up to 4 fully
independent external interrupt source sensitivities.
Each external interrupt source can be generated
on four (or five) different events on the pin:
s
Falling edge
s
Rising edge
s
Falling and rising edge
Falling edge and low level
s
Rising edge and high level (only for ei0 and ei2)
To guarantee correct functionality, the sensitivity
bits in the EICR register can be modified only
when the I1 and I0 bits of the CC register are both
set to 1 (level 3). This means that interrupts must
be disabled before changing sensitivity.
The pending interrupts are cleared by writing a dif-
ferent value in the ISx[1:0], IPA or IPB bits of the
EICR.
s
37/185

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