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ST72321AR6 Datasheet

  • ST72321AR6

  • 8-BIT MCU WITH NESTED INTERRUPTS, FLASH,10-BIT ADC, FIVE TIM...

  • 2302.91KB

  • STMicroelectronics   STMicroelectronics

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ST72321
INTERRUPTS
(Cont鈥檇)
7.5 INTERRUPT REGISTER DESCRIPTION
CPU CC REGISTER INTERRUPT BITS
Read /Write
Reset Value: 111x 1010 (xAh)
7
1
1
I1
H
I0
N
Z
0
C
ISPR1
I1_7
I0_7
I1_6
I0_6
I1_5
I0_5
I0_9
I1_4
I1_8
I0_4
I0_8
INTERRUPT SOFTWARE PRIORITY REGIS-
TERS (ISPRX)
Read/Write (bit 7:4 of
ISPR3
are read only)
Reset Value: 1111 1111 (FFh)
7
ISPR0
I1_3
I0_3
I1_2
I0_2
I1_1
I0_1
I1_0
0
I0_0
Bit 5, 3 =
I1, I0
Software Interrupt Priority
These two bits indicate the current interrupt soft-
ware priority.
Interrupt Software Priority
Level 0 (main)
Level 1
Level 2
Level 3 (= interrupt disable*)
Level
Low
I1
1
0
0
1
I0
0
1
0
1
ISPR2
ISPR3
I1_11 I0_11 I1_10 I0_10 I1_9
1
1
1
1
I1_13 I0_13 I1_12 I0_12
High
These two bits are set/cleared by hardware when
entering in interrupt. The loaded value is given by
the corresponding bits in the interrupt software pri-
ority registers (ISPRx).
They can be also set/cleared by software with the
RIM, SIM, HALT, WFI, IRET and PUSH/POP in-
structions (see 鈥淚nterrupt Dedicated Instruction
Set鈥?table).
*Note:
TLI, TRAP and RESET events can interrupt
a level 3 program.
These four registers contain the interrupt software
priority of each interrupt vector.
鈥?Each interrupt vector (except RESET and TRAP)
has corresponding bits in these registers where
its own software priority is stored. This corre-
spondance is shown in the following table.
Vector address
FFFBh-FFFAh
FFF9h-FFF8h
...
FFE1h-FFE0h
ISPRx bits
I1_0 and I0_0 bits*
I1_1 and I0_1 bits
...
I1_13 and I0_13 bits
鈥?Each I1_x and I0_x bit value in the ISPRx regis-
ters has the same meaning as the I1 and I0 bits
in the CC register.
鈥?Level 0 can not be written (I1_x=1, I0_x=0). In
this case, the previously stored value is kept. (ex-
ample: previous=CFh, write=64h, result=44h)
The TLI, RESET, and TRAP vectors have no soft-
ware priorities. When one is serviced, the I1 and I0
bits of the CC register are both set.
*Note:
Bits in the ISPRx registers which corre-
spond to the TLI can be read and written but they
are not significant in the interrupt process man-
agement.
Caution:
If the I1_x and I0_x bits are modified
while the interrupt x is executed the following be-
haviour has to be considered: If the interrupt x is
still pending (new interrupt or flag not cleared) and
the new software priority is higher than the previ-
ous one, the interrupt x is re-entered. Otherwise,
the software priority stays unchanged up to the
next interrupt request (after the IRET of the inter-
rupt x).
35/185

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