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ST72321AR6 Datasheet

  • ST72321AR6

  • 8-BIT MCU WITH NESTED INTERRUPTS, FLASH,10-BIT ADC, FIVE TIM...

  • 2302.91KB

  • STMicroelectronics   STMicroelectronics

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ST72321
INTERRUPTS
(Cont鈥檇)
7.3 INTERRUPTS AND LOW POWER MODES
All interrupts allow the processor to exit the WAIT
low power mode. On the contrary, only external
and other specified interrupts allow the processor
to exit from the HALT modes (see column 鈥淓xit
from HALT鈥?in 鈥淚nterrupt Mapping鈥?table). When
several pending interrupts are present while exit-
ing HALT mode, the first one serviced can only be
an interrupt with exit from HALT mode capability
and it is selected through the same decision proc-
ess shown in
Figure 19.
Note:
If an interrupt, that is not able to Exit from
HALT mode, is pending with the highest priority
when exiting HALT mode, this interrupt is serviced
after the first one serviced.
Figure 20. Concurrent Interrupt Management
TRAP
SOFTWARE
PRIORITY
LEVEL
IT2
IT1
IT4
IT3
IT0
I1
I0
7.4 CONCURRENT & NESTED MANAGEMENT
The following
Figure 20
and
Figure 21
show two
different interrupt management modes. The first is
called concurrent mode and does not allow an in-
terrupt to be interrupted, unlike the nested mode in
Figure 21.
The interrupt hardware priority is given
in this order from the lowest to the highest: MAIN,
IT4, IT3, IT2, IT1, IT0, TLI. The software priority is
given for each interrupt.
Warning:
A stack overflow may occur without no-
tifying the software of the failure.
HARDWARE PRIORITY
TRAP
IT0
IT1
IT2
IT3
RIM
IT4
MAIN
MAIN
IT1
3
3
3
3
3
3
3/0
10
1 1
1 1
1 1
1 1
1 1
1 1
11 / 10
Figure 21. Nested Interrupt Management
TRAP
SOFTWARE
PRIORITY
LEVEL
IT0
IT2
IT1
IT4
IT3
I1
I0
HARDWARE PRIORITY
TRAP
IT0
IT1
IT2
IT3
RIM
IT4
MAIN
IT4
MAIN
IT1
IT2
3
3
2
1
3
3
3/0
10
1 1
1 1
0 0
0 1
1 1
1 1
11 / 10
34/185
USED STACK = 20 BYTES
USED STACK = 10 BYTES

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