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ST72321AR6 Datasheet

  • ST72321AR6

  • 8-BIT MCU WITH NESTED INTERRUPTS, FLASH,10-BIT ADC, FIVE TIM...

  • STMicroelectronics   STMicroelectronics

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ST72321
SYSTEM INTEGRITY MANAGEMENT
(Cont鈥檇)
6.4.2.2 Monitoring a Voltage on the EVD pin
This mode is selected by setting the AVDS bit in
the SICSR register.
The AVD circuitry can generate an interrupt when
the AVDIE bit of the SICSR register is set. This in-
terrupt is generated on the rising and falling edges
of the comparator output. This means it is generat-
ed when either one of these two events occur:
鈥?V
EVD
rises up to V
IT+(EVD)
鈥?V
EVD
falls down to V
IT-(EVD)
The EVD function is illustrated in
Figure 16.
For more details, refer to the Electrical Character-
istics section.
Figure 16. Using the Voltage Detector to Monitor the EVD pin (AVDS bit=1)
V
EVD
V
IT+(EVD)
V
IT-(EVD)
V
hyst
AVDF
AVD INTERRUPT
REQUEST
IF AVDIE = 1
0
1
0
INTERRUPT PROCESS
INTERRUPT PROCESS
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