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ST72321AR6 Datasheet

  • ST72321AR6

  • 8-BIT MCU WITH NESTED INTERRUPTS, FLASH,10-BIT ADC, FIVE TIM...

  • STMicroelectronics   STMicroelectronics

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ST72321
SYSTEM INTEGRITY MANAGEMENT
(Cont鈥檇)
6.4.2 Auxiliary Voltage Detector (AVD)
The Voltage Detector function (AVD) is based on
an analog comparison between a V
IT-(AVD)
and
V
IT+(AVD)
reference value and the V
DD
main sup-
ply or the external EVD pin voltage level (V
EVD
).
The V
IT-
reference value for falling voltage is lower
than the V
IT+
reference value for rising voltage in
order to avoid parasitic detection (hysteresis).
The output of the AVD comparator is directly read-
able by the application software through a real
time status bit (AVDF) in the SICSR register. This
bit is read only.
Caution:
The AVD function is active only if the
LVD is enabled through the option byte.
6.4.2.1 Monitoring the V
DD
Main Supply
This mode is selected by clearing the AVDS bit in
the SICSR register.
The AVD voltage threshold value is relative to the
selected LVD threshold configured by option byte
(see
Section 14.1 on page 172).
If the AVD interrupt is enabled, an interrupt is gen-
erated when the voltage crosses the V
IT+(AVD)
or
V
IT-(AVD)
threshold (AVDF bit toggles).
In the case of a drop in voltage, the AVD interrupt
acts as an early warning, allowing software to shut
down safely before the LVD resets the microcon-
troller. See
Figure 15.
The interrupt on the rising edge is used to inform
the application that the V
DD
warning state is over.
If the voltage rise time t
rv
is less than 256 or 4096
CPU cycles (depending on the reset delay select-
ed by option byte), no AVD interrupt will be gener-
ated when V
IT+(AVD)
is reached.
If t
rv
is greater than 256 or 4096 cycles then:
鈥?If the AVD interrupt is enabled before the
V
IT+(AVD)
threshold is reached, then 2 AVD inter-
rupts will be received: the first when the AVDIE
bit is set, and the second when the threshold is
reached.
鈥?If the AVD interrupt is enabled after the V
IT+(AVD)
threshold is reached then only one AVD interrupt
will occur.
Figure 15. Using the AVD to Monitor V
DD
(AVDS bit=0)
V
DD
Early Warning Interrupt
(Power has dropped, MCU not
not yet in reset)
V
hyst
V
IT+(AVD)
V
IT-(AVD)
V
IT+(LVD)
V
IT-(LVD)
t
rv
VOLTAGE RISE TIME
AVDF bit
AVD INTERRUPT
REQUEST
IF AVDIE bit = 1
0
1
RESET VALUE
1
0
INTERRUPT PROCESS
INTERRUPT PROCESS
LVD RESET
28/185

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