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ST72321AR6 Datasheet

  • ST72321AR6

  • 8-BIT MCU WITH NESTED INTERRUPTS, FLASH,10-BIT ADC, FIVE TIM...

  • STMicroelectronics   STMicroelectronics

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ST72321
RESET SEQUENCE MANAGER
(Cont鈥檇)
The RESET pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteris-
tics section.
If the external RESET pulse is shorter than
t
w(RSTL)out
(see short ext. Reset in
Figure 13),
the
signal on the RESET pin may be stretched. Other-
wise the delay will not be applied (see long ext.
Reset in
Figure 13).
Starting from the external RE-
SET pulse recognition, the device RESET pin acts
as an output that is pulled low during at least
t
w(RSTL)out
.
6.3.3 External Power-On RESET
If the LVD is disabled by option byte, to start up the
microcontroller correctly, the user must ensure by
means of an external reset circuit that the reset
signal is held low until V
DD
is over the minimum
level specified for the selected f
OSC
frequency.
(see
鈥淥PERATING CONDITIONS鈥?on page 138)
A proper reset signal for a slow rising V
DD
supply
can generally be provided by an external RC net-
work connected to the RESET pin.
6.3.4 Internal Low Voltage Detector (LVD)
RESET
Two different RESET sequences caused by the in-
ternal LVD circuitry can be distinguished:
s
Power-On RESET
s
Voltage Drop RESET
The device RESET pin acts as an output that is
pulled low when V
DD
<V
IT+
(rising edge) or
V
DD
<V
IT-
(falling edge) as shown in
Figure 13.
The LVD filters spikes on V
DD
larger than t
g(VDD)
to
avoid parasitic resets.
6.3.5 Internal Watchdog RESET
The RESET sequence generated by a internal
Watchdog counter overflow is shown in
Figure 13.
Starting from the Watchdog counter underflow, the
device RESET pin acts as an output that is pulled
low during at least t
w(RSTL)out
.
Figure 13. RESET Sequences
V
DD
V
IT+(LVD)
V
IT-(LVD)
LVD
RESET
SHORT EXT.
RESET
LONG EXT.
RESET
WATCHDOG
RESET
RUN
ACTIVE PHASE
RUN
ACTIVE
PHASE
RUN
ACTIVE
PHASE
RUN
ACTIVE
PHASE
RUN
t
w(RSTL)out
t
h(RSTL)in
EXTERNAL
RESET
SOURCE
t
w(RSTL)out
t
h(RSTL)in
DELAY
t
w(RSTL)out
RESET PIN
WATCHDOG
RESET
WATCHDOG UNDERFLOW
INTERNAL RESET (256 or 4096 T
CPU
)
VECTOR FETCH
26/185

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