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ST72321AR6 Datasheet

  • ST72321AR6

  • 8-BIT MCU WITH NESTED INTERRUPTS, FLASH,10-BIT ADC, FIVE TIM...

  • 2302.91KB

  • STMicroelectronics   STMicroelectronics

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ST72321
6.3 RESET SEQUENCE MANAGER (RSM)
6.3.1 Introduction
The reset sequence manager includes three RE-
SET sources as shown in
Figure 12:
s
External RESET source pulse
s
Internal LVD RESET (Low Voltage Detection)
s
Internal WATCHDOG RESET
These sources act on the RESET pin and it is al-
ways kept low during the delay phase.
The RESET service routine vector is fixed at ad-
dresses FFFEh-FFFFh in the ST7 memory map.
The basic RESET sequence consists of 3 phases
as shown in
Figure 11:
s
Active Phase depending on the RESET source
s
256 or 4096 CPU clock cycle delay (selected by
option byte)
s
RESET vector fetch
The 256 or 4096 CPU clock cycle delay allows the
oscillator to stabilise and ensures that recovery
has taken place from the Reset state. The shorter
or longer clock cycle delay should be selected by
option byte to correspond to the stabilization time
of the external oscillator used in the application
(see
Section 14.1 on page 172).
Figure 12. Reset Block Diagram
The RESET vector fetch phase duration is 2 clock
cycles.
Figure 11. RESET Sequence Phases
RESET
Active Phase
INTERNAL RESET
256 or 4096 CLOCK CYCLES
FETCH
VECTOR
6.3.2 Asynchronous External RESET pin
The RESET pin is both an input and an open-drain
output with integrated R
ON
weak pull-up resistor.
This pull-up has no fixed value but varies in ac-
cordance with the input voltage. It can be pulled
low by external circuitry to reset the device. See
鈥淐ONTROL PIN CHARACTERISTICS鈥?on
page 160
for more details.
A RESET signal originating from an external
source must have a duration of at least t
h(RSTL)in
in
order to be recognized (see
Figure 13).
This de-
tection is asynchronous and therefore the MCU
can enter reset state even in HALT mode.
V
DD
R
ON
RESET
Filter
INTERNAL
RESET
PULSE
GENERATOR
WATCHDOG RESET
LVD RESET
25/185

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