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ST72321AR6 Datasheet

  • ST72321AR6

  • 8-BIT MCU WITH NESTED INTERRUPTS, FLASH,10-BIT ADC, FIVE TIM...

  • STMicroelectronics   STMicroelectronics

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ST72321
6 SUPPLY, RESET AND CLOCK MANAGEMENT
The device includes a range of utility features for
securing the application in critical situations (for
example in case of a power brown-out), and re-
ducing the number of external components. An
overview is shown in
Figure 10.
For more details, refer to dedicated parametric
section.
Main features
s
Optional PLL for multiplying the frequency by 2
(not to be used with internal RC oscillator)
s
Reset Sequence Manager (RSM)
s
Multi-Oscillator Clock Management (MO)
鈥?5 Crystal/Ceramic resonator oscillators
鈥?1 Internal RC oscillator
s
System Integrity Management (SI)
鈥?Main supply Low voltage detection (LVD)
鈥?Auxiliary Voltage detector (AVD) with interrupt
capability for monitoring the main supply or
the EVD pin
鈥?Clock Security System (CSS) with Clock Filter
and Backup Safe Oscillator (enabled by op-
Figure 10. Clock, Reset and Supply Block Diagram
SYSTEM INTEGRITY MANAGEMENT
CLOCK SECURITY SYSTEM
(CSS)
OSC2
OSC1
MULTI-
OSCILLATOR
(MO)
f
OSC
PLL
(option)
f
OSC2
CLOCK
FILTER
SAFE
OSC
f
OSC2
MAIN CLOCK
f
CPU
CONTROLLER
WITH REALTIME
CLOCK (MCC/RTC)
tion byte)
6.1 PHASE LOCKED LOOP
If the clock frequency input to the PLL is in the
range 2 to 4 MHz, the PLL can be used to multiply
the frequency by two to obtain an f
OSC2
of 4 to 8
MHz. The PLL is enabled by option byte. If the PLL
is disabled, then f
OSC2 =
f
OSC
/2.
Caution:
The PLL is not recommended for appli-
cations where timing accuracy is required. See
鈥淧LL Characteristics鈥?on page 150.
Figure 9. PLL Block Diagram
PLL x 2
f
OSC
0
f
OSC2
1
/2
PLL OPTION BIT
RESET SEQUENCE
RESET
MANAGER
(RSM)
AVD Interrupt Request
SICSR
AVD AVD AVD LVD
S IE
F RF
CSS CSS WDG
IE D RF
WATCHDOG
TIMER (WDG)
0
CSS Interrupt Request
LOW VOLTAGE
V
SS
V
DD
0
EVD
1
DETECTOR
(LVD)
AUXILIARY VOLTAGE
DETECTOR
(AVD)
23/185

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