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MAX1897 Datasheet

  • MAX1897

  • "Quick- PWM Slave Controllers for Multiphase, Step-Down Supp...

  • Maxim   Maxim

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Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
Ceramic Output Capacitor Applications
Ceramic capacitors have advantages and disadvan-
tages. They have ultra-low ESR and are noncom-
bustible, relatively small, and nonpolarized. However,
they are also expensive and brittle, and their ultra-low
ESR characteristic can result in excessively high ESR
zero frequencies. In addition, their relatively low capac-
itance value can cause output overshoot when step-
ping from full-load to no-load conditions, unless a small
inductor value is used (high switching frequency), or
there are some bulk tantalum or electrolytic capacitors
in parallel to absorb the stored inductor energy. In
some cases, there may be no room for electrolytics,
creating a need for a DC-DC design that uses nothing
but ceramics.
The MAX1887/MAX1897 can take full advantage of the
small size and low ESR of ceramic output capacitors in
a voltage-positioned circuit. The addition of the posi-
tioning resistor increases the ripple at FB, lowering the
effective ESR zero frequency of the ceramic output
capacitor.
Output overshoot (V
SOAR
) determines the minimum
output capacitance requirement (see the
Output
Capacitor Selection
section). Often the switching fre-
quency is increased to 550kHz, and the inductor value
is reduced to minimize the energy transferred from
inductor to capacitor during load-step recovery. The
efficiency penalty for operating at 550kHz is about 3%
when compared to the 300kHz circuit, primarily due to
the high-side MOSFET switching losses.
the master to the analog ground in the slave to pre-
vent ground offsets. A low value (鈮?0鈩? resistor is
sufficient to link the two grounds.
4) Keep the power traces and load connections short.
This is essential for high efficiency. The use of thick
copper PC boards (2oz vs. 1oz) can enhance full-load
efficiency by 1% or more. Correctly routing PC board
traces is a difficult task that must be approached in
terms of fractions of centimeters, where a single m鈩?/div>
of excess trace resistance causes a measurable effi-
ciency penalty.
5) Keep the high-current gate-driver traces (DL, DH,
LX, and BST) short and wide to minimize trace
resistance and inductance. This is essential for
high-power MOSFETs that require low-impedance
gate drivers to avoid shoot-through currents.
6) CS+, CS-, CM+, and CM- connections for current
limiting and balancing must be made using Kelvin
sense connections to guarantee the current-sense
accuracy.
7) When trade-offs in trace lengths must be made, it鈥檚
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it鈥檚 better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the low-side
MOSFET or between the inductor and the output filter
capacitor.
8) Route high-speed switching nodes away from sen-
sitive analog areas (COMP, ILIM). Make all pin-
strap control input connections (SHDN, ILIM, POL)
to analog ground or V
CC
rather than power ground
or V
DD
.
MAX1887/MAX1897
PC Board Layout Guidelines
Careful PC board layout is critical to achieve low
switching losses and clean, stable operation. The
switching power stage requires particular attention
(Figure 9). If possible, mount all of the power compo-
nents on the top side of the board with their ground ter-
minals flush against one another. Follow these
guidelines for good PC board layout:
1) Keep the high-current paths short, especially at the
ground terminals. This is essential for stable, jitter-
free operation
2) Connect all analog grounds to a separate solid
copper plane, which connects to the GND pin of
the MAX1887/MAX1897. This includes the V
CC
bypass capacitor, COMP components, and the
resistive-divider connected to ILIM.
3) The master controller also should have a separate
analog ground. Return the appropriate noise sensi-
tive components to this plane. Since the reference
in the master is sometimes connected to the slave,
it may be necessary to couple the analog ground in
Layout Procedure
1) Place the power components first, with ground termi-
nals adjacent (low-side MOSFET source, C
IN
, C
OUT
,
and D1 anode). If possible, make all these connec-
tions on the top layer with wide, copper-filled areas.
2) Mount the controller IC adjacent to the low-side
MOSFET. The DL gate trace must be short and
wide (50mils to 100mils wide if the MOSFET is 1
inch from the controller IC).
3) Group the gate-drive components (BST diode and
capacitor, V
DD
bypass capacitor) together near the
controller IC.
4) Make the DC-DC controller ground connections as
shown in Figure 1. This diagram can be viewed as
having four separate ground planes: input/output
ground, where all the high-power components go;
the power ground plane, where the PGND pin and
27
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