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MAX1897 Datasheet

  • MAX1897

  • "Quick- PWM Slave Controllers for Multiphase, Step-Down Supp...

  • Maxim   Maxim

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Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
V
IN(MAX)
, consider choosing another MOSFET with
lower parasitic capacitance.
For the low-side MOSFET (N
L
), the worst-case power
dissipation always occurs at maximum input voltage:
2
錚?錚?/div>
V
錚?錚癸＋
I
OUT
LOAD
錚?/div>
R
PD(N
L
Re sistive)
= 錚?/div>
1
鈭?/div>
錚?/div>
錚?/div>
DS(ON)
錚?錚猴，
錚?錚?/div>
V
IN(MAX)
錚?錚猴－ 畏 錚?/div>
錚?/div>
錚?/div>
Balancing
section). To reduce noise pick-up in applica-
tions that have a widely distributed layout, it is some-
times helpful to connect the compensation network to
quiet analog ground rather than V
OUT
.
MAX1887/MAX1897
Applications Information
Voltage Positioning and
Effective Efficiency
Powering new mobile processors requires careful
attention to detail to reduce cost, size, and power dissi-
pation. As CPUs became more power hungry, it was
recognized that even the fastest DC-DC converters
were inadequate to handle the transient power require-
ments. After a load transient, the output instantly
changes by ESR
COUT
鉁?/div>
鈭咺
LOAD
. Conventional DC-DC
converters respond by regulating the output voltage
back to its nominal state after the load transient occurs
(Figure 7). However, the CPU only requires that the out-
put voltage remain above a specified minimum value.
Dynamically positioning the output voltage to this lower
limit allows the use of fewer output capacitors and
reduces power consumption under load.
For a conventional (nonvoltage-positioned) circuit, the
total voltage change is:
V
P-P
1 = 2
鉁?/div>
(ESR
COUT
鉁?/div>
鈭咺
LOAD
) + V
SAG
+ V
SOAR
where V
SAG
and V
SOAR
are defined in Figure 8. Setting
the converter to regulate at a lower voltage when under
load allows a larger voltage step when the output cur-
rent suddenly decreases (Figure 7). So the total voltage
change for a voltage-positioned circuit is:
V
P-P
2 = (ESR
COUT
鉁?/div>
鈭咺
LOAD
) + V
SAG
+ V
SOAR
where V
SAG
and V
SOAR
are defined in the
Design
Procedure
section. Since the amplitudes are the same
for both circuits (V
P-P
1 = V
P-P
2), the voltage-positioned
circuit tolerates twice the ESR. Since the ESR specifica-
tion is achieved by paralleling several capacitors, fewer
units are needed for the voltage-positioned circuit.
An additional benefit of voltage positioning is reduced
power consumption at high load currents. Since the
output voltage is lower under load, the CPU draws less
current. The result is lower power dissipation in the
CPU, although some extra power is dissipated in
R
SENSE
. For a nominal 1.6V, 22A output (R
LOAD
=
72.7m鈩?, reducing the output voltage 2.9% gives an
output voltage of 1.55V and an output current of 21.3A.
Given these values, CPU power consumption is
reduced from 35.2W to 33.03W. The additional power
consumption of R
SENSE
is:
The worst case for MOSFET power dissipation occurs
under heavy overloads that are greater than
I
LOAD(MAX)
but are not quite high enough to exceed
the current limit and cause the fault latch to trip. To pro-
tect against this possibility, 鈥渙verdesign鈥?the circuit to
tolerate:
錚?/div>
I
LOAD(MAX)
LIR
錚?/div>
I
LOAD
= 畏
I
VALLEY(MAX)
+ 錚?/div>
錚?/div>
2
錚?/div>
錚?/div>
where I
VALLEY(MAX)
is the maximum valley current
allowed by the current-limit circuit, including threshold
tolerance and on-resistance variation. The MOSFETs
must have a good-sized heatsink to handle the over-
load power dissipation.
Choose a Schottky diode (D1) with a forward voltage
low enough to prevent the low-side MOSFET body
diode from turning on during the dead time. As a gen-
eral rule, select a diode with a DC current rating equal
to 1/(3
畏
) of the load current. This diode is optional and
can be removed if efficiency is not critical.
Current Balance Compensation (COMP)
The current balance compensation capacitor (C
COMP
)
integrates the difference of the master and slave cur-
rent-sense signals, while the compensation resistor
improves transient response by increasing the phase
margin. This allows the user to optimize the dynamics
of the current balance loop. Excessively large capacitor
values increase the integration time constant, resulting
in larger current differences between the phases during
transients. Excessively small capacitor values allow the
current loop to respond cycle by cycle but can result in
small DC current variations between the phases.
Likewise, excessively large series resistance can also
cause DC current variations between the phases. Small
series resistance reduces the phase margin, resulting
in marginal stability in the current balance loop. For
most applications, a 470pF capacitor and 10k鈩?series
resistor from COMP to the converter鈥檚 output voltage
works well.
The compensation network can be tied to V
OUT
to
include the feed-forward term due to the master鈥檚 on
time (see the
On-time Control and Active Current
______________________________________________________________________________________
25

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