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T48C862-R8 Datasheet

  • T48C862-R8

  • MCU

  • 1463.36KB

  • Atmel   Atmel

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Figure 65.
Example of 8-bit Synchronous Transmit Operation
SC
msb
SD
lsb
0
msb
lsb msb
lsb
0
7 6 5 4 3 2 1
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1
tx data 1
SIR
tx data 2
tx data 3
SRDY
ACT
Interrupt
(IFN = 0)
Interrupt
(IFN = 1)
Write STB
(tx data 1)
Write STB
(tx data 2)
Write STB
(tx data 3)
Figure 66.
Example of 8-bit Synchronous Receive Operation
SC
msb
SD
lsb
msb
lsb
msb
lsb
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
rx data 1
rx data 2
7 6 5 4 3 2 1 0 7 6 5 4
rx data 3
SIR
SRDY
ACT
Interrupt
(IFN = 0)
Interrupt
(IFN = 1)
Read SRB
(rx data 1)
Read SRB
(rx data 2)
Read SRB
(rx data 3)
9-bit Shift Mode
(MCL compatible)
In the 9-bit shift mode, the SSI is able to handle the MCL protocol (described below). It
always operates as an MCL master device, i.e., SC is always generated and output by
the SSI. Both the MCL start and stop conditions are automatically generated whenever
the SSI is activated or deactivated by the SIR-bit. In accordance with the MCL protocol,
the output data is always changed in the clock low phase and shifted in on the high
phase.
Before activating the SSI (SIR = 0) and commencing an MCL dialog, the appropriate
data direction for the first word must be set using the SDD control bit. The state of this
70
T48C862-R8
4590B鈥?BMCU鈥?2/03

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