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T48C862-R8 Datasheet

  • T48C862-R8

  • MCU

  • 1463.36KB

  • Atmel   Atmel

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T48C862-R8
Figure 4.
Tolerances of Frequency Modulation
~
V
S
C
Stray1
XTAL
C
Stray2
C
M
L
M
C
0
Crystal equivalent circuit
R
S
C
4
C
5
C
Switch
Using C
4
= 9.2 pF 鹵2%, C
5
= 6.8 pF 鹵5%, a switch port with C
Switch
= 3 pF 鹵10%, stray
capacitances on each side of the crystal of C
Stray1
= C
Stray2
= 1 pF 鹵10%, a parallel
capacitance of the crystal of C
0
= 3.2 pF 鹵10% and a crystal with C
M
= 13 fF 鹵10%, an
FSK deviation of 鹵21 kHz typical with worst case tolerances of 鹵16.3 kHz to 鹵28.8 kHz
results.
~
CLK Output
Clock Pulse Take Over
An output CLK signal is provided for a connected microcontroller. The delivered signal is
CMOS compatible if the load capacitance is lower than 10 pF.
The clock of the crystal oscillator can be used for clocking the microcontroller. Atmel鈥檚
M4xCx9x has the special feature of starting with an integrated RC-oscillator to switch on
the PLL transmitter block with ENABLE = H, and after 4 ms to assume the clock signal
of the transmission IC, so the message can be sent with crystal accuracy.
The output power is set by the load impedance of the antenna. The maximum output
power is achieved with a load impedance of Z
Load,opt
= (166 + j226)
W
at 868.3 MHz.
There must be a low resistive path to V
S
to deliver the DC current.
The delivered current pulse of the power amplifier is 7.7 mA and the maximum output
power is delivered to a resistive load of 475
W
if the 0.53 pF output capacitance of the
power amplifier is compensated by the load impedance.
An optimum load impedance of:
Z
Load
= 475
W
|| j/(2
麓 p 麓f 麓
0.53 pF) = (166 + j226)
W
thus results for the maximum out-
put power of 5.5 dBm.
The load impedance is defined as the impedance seen from the PLL transmitter block鈥檚
ANT1, ANT2 into the matching network. Do not confuse this large signal load imped-
ance with a small signal input impedance delivered as input characteristic of RF
amplifiers and measured from the application into the IC instead of from the IC into the
application for a power amplifier.
Less output power is achieved by lowering the real parallel part of 475
W
where the
parallel imaginary part should be kept constant.
Output power measurement can be done with the circuit shown in Figure 5. Note that
the component values must be changed to compensate the individual board parasitics
until the PLL transmitter block has the right load impedance Z
Load,opt
= (166 + j226)
W
at
868.3 MHz. Also the damping of the cable used to measure the output power must be
calibrated.
Output Matching and Power
Setting
7
4590B鈥?BMCU鈥?2/03

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