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T48C862-R8 Datasheet

  • T48C862-R8

  • MCU

  • Atmel   Atmel

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The 4-bit stage is used as programmable prescaler for the 8-bit counter stage. In this
mode, a duty cycle stage is also available. This stage can be used as an additional 2-bit
prescaler or for generating duty cycles of 25%, 33% and 50%. The 4-bit compare output
(CM1) supplies the clock output (POUT) with clocks.
Mode 3/4: 8-bit Compare
Counter and 4-bit
Programmable Prescaler
Figure 38.
4-/8-bit Compare Counter
DCGO
T2I
SYSCL
CL2/2
OVF2
TOG2
DCG
8-bit counter
RES
INT4
CM2
Timer 2
output mode
and T2OTM-bit
P4CR
P41M2, 1
T2D1, 0
8-bit compare
8-bit register
T2RM
T2OTM
T2IM
T2CTM
TOG3
T1OUT
SYSCL
SCL
MUX
CL2/1
4-bit counter
RES
CM1
POUT
4-bit compare
T2CS1, 0
4-bit register
In these modes the 4-bit and the 8-bit counter stages work independently as a 4-bit
prescaler and an 8-bit timer with an 2-bit prescaler or as a duty cycle generator. Only in
the mode 3 and mode 4, can the 8-bit counter be supplied via the external clock input
(T2I) which is selected via the P4CR register. The 4-bit prescaler is started via activating
of mode 3 and stopped and reset in mode 4. Changing mode 3 and 4 has no effect for
the 8-bit timer stage. The 4-bit stage can be used as prescaler for Timer 3, the SSI or to
generate the stop signal for modulator 2 and modulator 3.
Timer 2 Output Modes
The signal at the timer output is generated via modulator 2. In the toggle mode, the com-
pare match event toggles the output T2O. For high resolution duty cycle modulation 8
bits or 12 bits can be used to toggle the output. In the duty cycle burst modulator modes
the DCG output is connected to T2O and switched on and off either by the toggle flipflop
output or the serial data line of the SSI. Modulator 2 also has two modes to output the
content of the serial interface as Biphase or Manchester code.
The modulator output stage can be configured by the output control bits in the T2M2
register. The modulator is started with the start of the shift register (SIR = 0) and
stopped either by carrying out a shift register stop (SIR = 1) or compare match event of
stage 1 (CM1) of Timer 2. For this task, Timer 2 mode 3 must be used and the prescaler
has to be supplied with the internal shift clock (SCL).
46
T48C862-R8
4590B鈥?BMCU鈥?2/03

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