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T48C862-R8 Datasheet

  • T48C862-R8

  • MCU

  • Atmel   Atmel

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T48C862-R8
Timer 1 Control Register 2
(T1C2)
Bit 3 *
---
Bit 2
T1BP
Bit 1
T1CS
Bit 0
T1IM
Reset value: x111b
Address: "7"hex - Subaddress: "9"hex
* Bit 3 -> MSB, Bit 0 -> LSB
T1BP
Timer 1
SUBCL
ByPassed
T1BP = 1, TIOUT = T1MUX
T1BP = 0, T1OUT = SUBCL
Timer 1
input
Clock Select
T1CS = 1, CL1 = SUBCL (see Figure 27)
T1CS = 0, CL1 = SYSCL (see Figure 27)
Timer 1 Interrupt Mask
T1IM = 1, disables Timer 1 interrupt
T1IM = 0, enables Timer 1 interrupt
T1CS
T1IM
Watchdog Control Register
(WDC)
Bit 3 *
WDL
Bit 2
WDR
Bit 1
WDT1
Bit 0
WDT0
Address: "7"hex - Subaddress: "A"hex
Reset value: 1111b
* Bit 3 -> MSB, Bit 0 -> LSB
WDL
WatchDog Lock
mode
WDL = 1, the watchdog can be enabled and disabled by using the WDR-bit
WDL = 0, the watchdog is enabled and locked. In this mode the WDR-bit has no
effect. After the WDL-bit is cleared, the watchdog is active until a
system reset or power-on reset occurs.
WatchDog Run
and stop mode
WDR = 1, the watchdog is stopped/disabled
WDR = 0, the watchdog is active/enabled
WatchDog Time 1
WatchDog Time 0
WDR
WDT1
WDT0
Both these bits control the time interval for the watchdog reset.
Delay Time to Reset with
SUBCL = 32 kHz
15.625 ms
62.5 ms
0.5 s
4s
Delay Time to Reset with
SYSCL = 2/1 MHz
0.256 ms/0.512 ms
1.024 ms/2.048 ms
8.2 ms/16.4 ms
65.5 ms/131 ms
WDT1
0
0
1
1
WDT0
0
1
0
1
Divider
512
2048
16384
131072
43
4590B鈥?BMCU鈥?2/03

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