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T48C862-R8 Datasheet

  • T48C862-R8

  • MCU

  • Atmel   Atmel

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T48C862-R8
Timer 1 can also be used as a watchdog timer to prevent a system from stalling. The
watchdog timer is a 3-bit counter that is supplied by a separate output of Timer 1. It gen-
erates a system reset when the 3-bit counter overflows. To avoid this, the 3-bit counter
must be reset before it overflows. The application software has to accomplish this by
reading the CWD register.
After power-on reset the watchdog must be activated by software in the $RESET initial-
ization routine. There are two watchdog modes, in one mode the watchdog can be
switched on and off by software, in the other mode the watchdog is active and locked.
This mode can only be stopped by carrying out a system reset.
The watchdog timer operation mode and the time interval for the watchdog reset can be
programmed via the watchdog control register (WDC).
Figure 33.
Timer 1 Module
SYSCL
SUBCL
WDCL
MUX
CL1
Prescaler
14 bit
Watchdog
4 bit
NRST
INT2
T1CS
T1MUX
T1BP
T1IM
T1OUT
Figure 34.
Timer 1 and Watchdog
T1C1 T1RM T1C2 T1C1 T1C0
3
Write of the
T1C1 register
T1IM=0
T1MUX
T1C2
T1BP T1IM
Decoder
MUX for interval timer
T1IM=1
INT2
T1OUT
RES Q1 Q2 Q3 Q4 Q5
CL1
CL
Q6
Q8
Q8
Q11
Q11
Q14 SUBCL
Q14
Watchdog
Divider / 8
Decoder
2
WDL
WDR WDT1 WDT0
MUX for watchdog timer
WDCL
RES
Read of the
CWD register
Divider
RESET
RESET
(NRST)
WDC
Watchdog
mode control
41
4590B鈥?BMCU鈥?2/03

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