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SC28L194 Datasheet

  • SC28L194

  • Quad UART for 3.3V and 5V supply

  • Philips

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Philips Semiconductors
Preliminary specification
Quad UART for 3.3V and 5V supply voltage
SC28L194
Interrupt Control
The interrupt system determines when an interrupt should be
asserted thorough an arbitration (or bidding) system. This arbitration
is exercised over the several systems within the QUART that may
generate an interrupt. These will be referred to as 鈥渋nterrupt
sources鈥? There are 64 in all. In general the arbitration is based on
the fill level of the receiver FIFO or the empty level of the transmitter
FIFO. The FIFO levels are encoded into a four bit number which is
concatenated to the channel number and source identification code.
All of this is compared (via the bidding or arbitration process) to a
user defined 鈥渢hreshold鈥? When ever a source exceeds the
numerical value of the threshold the interrupt will be generated.
At the time of interrupt acknowledge (IACKN) the source which has
the highest bid (not necessarily the source that caused the interrupt
to be generated) will be captured in a 鈥淐urrent Interrupt Register鈥?/div>
(CIR). This register will contain the complete definition of the
interrupting source: channel, type of interrupt (receiver, transmitter,
change of state, etc.), and FIFO fill level. The value of the bits in the
CIR are used to drive the interrupt vector and global registers such
that controlling processor may be steered directly to the proper
service routine. A single read operation to the CIR provides all the
information needed to qualify and quantify the most common
interrupt sources.
The interrupt sources for each channel are listed below.
Each of the four pins has a change of state detector which will signal
a change (0 to 1 or 1 to 0) at the pin. The change of state detectors
are individually enabled and may be set to cause and interrupt.
These pins will normally be used for flow control hand-shaking and
the interface to a modem. Their control is further described in
I/O
Ports
section and the I/OPCR register.
DETAILED DESCRIPTIONS
RECEIVER AND TRANSMITTER
The Quad UART has four full duplex asynchronous
receiver/transmitters. The operating frequency for the receiver and
transmitter can be selected independently from the baud rate
generator, the counter , or from an external input. Registers that are
central to basic full-duplex operation are the mode registers (MR0,
MR1 and MR2), the clock select registers (RxCSR and TxCSR), the
command register (CR), the status register (SR), the transmit
holding register (TxFIFO), and the receive holding register
(RxFIFO).
Transmitter
The transmitter accepts parallel data from the CPU and converts it
to a serial bit stream on the TxD output pin. It automatically sends a
start bit followed by the programmed number of data bits, an
optional parity bit, and the programmed number of stop bits. The
least significant bit is sent first. Each character is always 鈥渇ramed鈥?by
a single start bit and a stop bit that is 9/16 bit time or longer. If a new
character is not available in the TxFIFO, the TxD output remains
high, the 鈥渕arking鈥?position, and the TxEMT bit in the SR is set to 1.
Transmitter Status Bits
The SR (Status Register, one per UART) contains two bits that show
the condition of the transmitter FIFO. These bits are TxRDY and
TxEMT. TxRDY means the TxFIFO has space available for one or
more bytes; TxEMT means The TxFIFO is completely empty and
the last stop bit has been completed. TxEMT can not be active
without TxRDY also being active. These two bits will go active upon
initial enabling of the transmitter. They will extinguish on the disable
or reset of the transmitter.
Transmission resumes and the TxEMT bit is cleared when the CPU
loads at least one new character into the TxFIFO. The TxRDY will
not extinguish until the TxFIFO is completely full. The TxRDY bit will
always be active when the transmitter is enabled and there is at
lease one open position in the TxFIFO.
The transmitter is disabled by reset or by a bit in the command
register (CR). The transmitter must be explicitly enabled via the CR
before transmission can begin. Note that characters cannot be
loaded into the TxFIFO while the transmitter is disabled, hence it is
necessary to enable the transmitter and then load the TxFIFO. It is
not possible to load the TxFIFO and then enable the transmission.
Note the difference between transmitter disable and transmitter
reset. The reset is affected by either software or hardware. When
reset, the transmitter stops transmission immediately. The transmit
data output will be driven high, transmitter status bits set to zero and
any data remaining in the TxFIFO will be discarded.
The transmitter disable is controlled by the Tx Enable bit in the
command register. Setting this bit to zero will not stop the transmitter
immediately, but will allow it to complete any tasks presently
underway. It is only when the last character in the TxFIFO and its
stop bit(s) have been transmitted that the transmitter will go to its
disabled state. While the transmitter enable/disable bit in the
command register is at zero, the TxFIFO will not accept any
additional characters.
7
鈥?/div>
Transmit FIFO empty level for each channel
鈥?/div>
Receive FIFO Fill level for each channel
鈥?/div>
Change in break received status for each channel
鈥?/div>
Receiver with error for each channel
鈥?/div>
Change of state on channel input pins
鈥?/div>
Receiver Watch-dog Time out Event
鈥?/div>
Xon/Xoff character recognition
鈥?/div>
Address character recognition
Associated with the interrupt system are the interrupt mask register
(IMR) and the interrupt status register (ISR) resident in each UART.
Programming of the IMR selects which of the above sources may
enter the arbitration process. Only the bidders in the ISR whose
associated bit in the IMR is set to one (1) will be permitted to enter
the arbitration process. The ISR can be read by the host CPU to
determine all currently active interrupting conditions. For
convenience the bits of the ISR may be masked by the bits of the
IMR. Whether the ISR is read unmasked or masked is controlled by
the setting of bit 6 in MR1.
Global Registers
The 鈥淕lobal Registers鈥? 19 in all, are driven by the interrupt system.
These are not real hardware devices. They are defined by the
content of the CIR (Current Interrupt Register) as a result of an
interrupt arbitration. In other words they are indirect registers
contained in the Current Interrupt Register (CIR) which the CIR uses
to point to the source and context of the QUART sub circuit
presently causing an interrupt. The principle purpose of these
鈥渞egisters鈥?is improving the efficiency of the interrupt service.
The global registers and the CIR update procedure are further
described in the
Interrupt Arbitration
system
I/O Ports
Each of the four UART blocks contains an I/O section of four ports.
These ports function as a general purpose post section which
services the particular UART they are associated with. External
clocks are input and internal clocks are output through these ports.
1998 Sep 21

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