Philips Semiconductors
Preliminary specification
Quad UART for 3.3V and 5V supply voltage
SC28L194
T/RF
SCLK
t
SCLKL
t
SCLKH
f
SCLK
SD00199
Figure 10. SCLK Timing
T/RF
SCLK
TC/TL
TC/TH
FC/T
TC/TO
SD00200
Figure 11. Counter/Timer Baud Rate Clock, External
T/RF
Trx
Ttx
TC/TH
Frx
Ftx
TC/TO
SD00201
Figure 12. Tx/Rx Clock Timing, External
1X DATA CLOCK
t
RXH
RxD
t
TXD
TxD
t
RXS
SD00202
Figure 13. Transmitter and Receiver Timing
Note: CEN
must
not be active during an IACKN cycle. If CEN is
active IACKN will be ignored and a normal read or write will be
executed according to W_RN.
In the synchronous mode extended IACKN signal cycle will start
another IACKN. (This may not be desired, but is allowed.)
1998 Sep 21
46