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SC28L194 Datasheet

  • SC28L194

  • Quad UART for 3.3V and 5V supply

  • Philips

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Philips Semiconductors
Preliminary specification
Quad UART for 3.3V and 5V supply voltage
SC28L194
C1
SCLK
C2
C3
C4
IACKN
CEN
W_RN
DON鈥橳 CARE
ADDRESS
INVALID
DON鈥橳 CARE
INVALID
DATA
DACKN
t
CS
INVALID
VALID
INVALID
t
AS
t
RWS
t
AH
t
DF
t
DD
C4
DAK
DLY
DAK
DLY
CEN
HIGH
NOTE: CEN must not be active during an IACKN cycle. If CEN is active, IACKN will be ignored
and a normal read or write will be executed according to W_RN. In the synchronous
mode, extended IACKN signal will start another IACKN. (This may not be desired, but
is allowed.)
SD00525
Figure 8. Basic IACKN Cycle, ASYNC/SYNC
+5V
T/R f
X1
X1 L/H
1K required for
TTL gate.
X1
f
X1
NC
X2
C1 = C2 = 24pF FOR C
L
= 20pF
C1 and C2 should be chosen according to the
crystal manufacturer鈥檚 specification.
C1 and C2 values will include any parasitic
capacitance of the wiring.
C1
28C194
X1
BRG
3pF
50 KOHMs
TO
150 KOHMs
X2
3.6864MHz
4pF
MUX
梅
2
To
remainder
of circuit
22
STANDARD
BAUD
RATES
C2
38.4kHz CLOCK
TO I/O CHANGE-OF-STATE DETECTORS
NOTES:
C1 and C2 should be based on manufacturer鈥檚 specification.
X1 and X2 parasitic capacitance IS 1-2pF AND 3-5pF, respectively.
GAIN: at 4MHz 8 to 14db; at 8MHz 2 to 6db
PHASE: at 4MHz 272擄 to 276擄; at 8MHz 272擄 to 276擄
The above figures for 5V operation. Operation at 3V is to be determined.
TYPICAL CRYSTAL SPECIFICATION
FREQUENCY:
2 鈥?4MHZ
12 鈥?32pF
LOAD CAPACITANCE (C
L
):
TYPE OF OPERATION:
PARALLEL RESONANT, FUNDAMENTAL MODE
SD00670
Figure 9. X1/X2 Communication Crystal Clock
1998 Sep 21
45

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