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SC28L194 Datasheet

  • SC28L194

  • Quad UART for 3.3V and 5V supply

  • Philips

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Philips Semiconductors
Preliminary specification
Quad UART for 3.3V and 5V supply voltage
SC28L194
AC ELECTRICAL SPECIFICATIONS FOR COMMERCIAL AND INDUSTRIAL (5V)
(continued)
V
CC
= 5.0V
鹵
10%, 鈥?0 to +85擄C
SYMBOL
Sclk Timing
t
sclkl
t
sclkh
F
sclk
t/
RFsck
Fx1
5
X1 L / H
T/RFx1
FC/T
4
TC/TLH
TC/TO
DTACK Timing
DAKdly
DAKdlya
DAKdlys
tgpirtx
DACK low from Sclk C4 rising edge
DACK high from CEN high (Async)
DACK high from C4 end rising edge (Sync)
GPI to Rx/Tx clock out
RxD setup to I/OP rising edge 1X mode
I/OP falling edge to TxD out 1X mode
Gout Timing
GPOtdd
GPO valid after write to GPOR
100
ns
NOTES:
1. Timing is illustrated and referenced with respect to W-RN and CEN inputs. Internal read and write activities are controlled by the Sclk as it
generates the several 鈥淐鈥?timing as shown in the timing diagrams.
2. The minimum time before the rising edge of the next C2 time to stop the next bus cycle. CEN must return high after midpoint of C4 time and
before the C2 time of the next cycle.
3. Delay is from cEN high in Async mode to IRQN inactive, from end of C4 to IRQN inactive in sync mode.
4. The minimum frequency values are not tested, but are guaranteed by design.
5. 1MHz specification is for crystal operation.
20
10
11
11
32
2
32
60
18
20
20
50
ns
ns
ns
ns
ns
ns
Min low time at V
IL
(0.8V)
Min high time at V
IH
(2.0V)
Sclk frequency
Sclk rise and fall time (0.8 to 2.0 Volts)
X1 clock frequency
X1 Low / High time
X1 Rise and Fall time
Clock frequency
C/T high and low time
Delay C/T clock external to output pin
0
15
11
48
60
1
32
3.6864
125
10
8
11
11
0.1
5
5
33
3
8.0
ns
ns
MHz
ns
MHz
ns
ns
MHz
ns
ns
FIG.
FIG #
PARAMETER
LIMITS
MIN.
TYP.
MAX.
UNIT
X1/X2 Communication Crystal Clock
Counter/Timer Baud Rate Clock (External Clock Input)
I/O Port External Clock
1998 Sep 21
42

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