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SC28L194 Datasheet

  • SC28L194

  • Quad UART for 3.3V and 5V supply

  • Philips

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Philips Semiconductors
Preliminary specification
Quad UART for 3.3V and 5V supply voltage
SC28L194
AC ELECTRICAL SPECIFICATIONS FOR COMMERCIAL AND INDUSTRIAL (3.3V)
V
CC
= 3.3V
鹵
10%, 鈥?0 to +85擄C
SYMBOL
Reset Timing
t
RES1
Bus Timing
t
AS
t
AH
t
CS
t
C
CH
t
STP
t
RWS
t
RWH
t
DD
t
DF
t
DS
t
DH
t
RWD
I/O Port Pin Timing
t
PS
t
PH
t
PD
Interrupt Timing
IRQN from:
Internal interrupt source active bid
Reset to IRQN inactive
Write IMR (set or clear IMR bit)
3
Interrupt vector valid after C3 rising edge
RxC high or low time
RxC frequency
TxC high or low time
TxC frequency
(16 X)
(1 X)
(16 X)
(1 X)
20
0
0
20
0
0
50
鈥?5
25
25
17/32
4
14
14
7
8
1
90
15
22
26
60
40
20
8
8
1
43
90
60
30
Sclk
ns
ns
ns
ns
MHz
MHz
ns
MHz
MHz
ns
ns
ns
ns
bit time
I/O input setup time before Sclk C3 falling edge (Read IPR)
I/O input hold time after Sclk C4 rising edge
I/O output valid from:
Write Sclk C4 rising edge (write to IOPIOR)
18
12
4
4
50
80
ns
ns
ns
A0鈥揂7 setup time before Sclk C3 rising edge
A0鈥揂7 hold time after Sclk C3 rising edge
CEN setup time before Sclk C1 high (Async)
CEN setup time before Sclk C2 high (Sync)
CEN hold time after Sclk C3 high (Sync)
CEN hold time after Sclk C4 high (Async)
CEN high before next C2 to stop next cycle (Sync Mode)
2
W鈥揜n setup time before Sclk C2 rising edge
W鈥揜n hold time after Sclk C3 rising edge
Read cycle Data valid after Sclk C3 falling edge
Read cycle data bus floating after CEN high (Async)
Read cycle data bus floating after C4 end (Sync)
Write cycle data setup time before Sclk C4 rising edge
Write cycle data hold time after Sclk C4 rising edge
High time between CEN low (Async)
25
25
15
15
30
7
7
25
50
30
7
25
1
1
/
2
Sclk
20
17
11
14
14
1
/ Sclk
2
FIG.
FIG #
PARAMETER
LIMITS
MIN.
10
3
12
3
3
1
1
/
2
Sclk
1
1
/
2
Sclk
TYP.
MAX.
UNIT
RESET pulse width
Sclk
ns
ns
ns
ns
ns
ns
ns
ns
ns
40
30
20
ns
ns
ns
ns
ns
ns
t
IR
t
DD
Tx/Rx Clock Timing
t
RX
f
RX4
t
TX
f
TX4
Transmitter Timing
t
TXD
t
TCS
Receiver Timing
t
RXS
t
RXH
ts
STRT
TxD output delay from TxC low
TxC output delay from TxD output data
RxD data setup time to RxC high (data)
RxD data hold time from RxC high (data)
RxD data low time for receiving a valid Start Bit
1998 Sep 21
38

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