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SC28L194 Datasheet

  • SC28L194

  • Quad UART for 3.3V and 5V supply

  • Philips

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Philips Semiconductors
Preliminary specification
Quad UART for 3.3V and 5V supply voltage
SC28L194
REGISTER MAPS
The registers of the SC28L194 are partitioned into two groups: those
used in controlling data channels and those used in handling the
actual data flow and status. Below is shown the general
configuration of all the register addressed. The 鈥淩egister Map
Summary鈥?shows the configuration of the lower four bits of the
address that is the same for the individual UARTs. It also shows the
addresses for the several in the address space of UART A and
UART B that apply to the total chip configuration. The 鈥淩egister Map
Detail鈥?shows the use of every address in the 8-bit address space.
NOTE: The register maps for channels A and B (UARTs A and B)
contain some control registers that configure the entire chip.
These
are denoted by a
鈾?/div>
symbol
REGISTER MAP SUMMARY
Table 43. Summary Register Map, Control
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Address (hex) ccc = channel
Register Name
Acronym
MR0
MR1
Read / Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Page
17
18
28
24
24
24
24
24
24
24
20
20
16
26
25
27
0ccc 0000 (x00)
0ccc 0001 (x01)
0ccc 0010 (x02)
0ccc 0011 (x03)
0ccc 0110 (x06)
0ccc 0111 (x07)
0ccc 0100 (x04)
Mode Register 0 MR0a
Mode Register 1 MR1a
I/O Port Configuration Reg a I/OPCRa
Bid Control, Break Change
Bid Control, Xon/Xoff
Bid Control, Change of State
IOPCR
BCRBRK
BCRX
BCRA
BCRCOS
Bid Control, Address recognition
Xon Character Register
Xoff Character Register
0ccc 1000 (x08)
0ccc 1001 (x09)
XonCR
XoffCR
ARCR
0ccc 1010 (x0A)
0ccc 1100 (x0C)
0ccc 1110 (x0E)
Address Recognition Character
Receiver Clock Select Register
鈾?/div>
Test Register
RxCSR
TxCSR
GCCR
ICR
IVR
0000 1101 (x0D)
0000 1111 (x0F)
Reserved, set to 0
Transmitter Clock Select Register
鈾?/div>
Interrupt Control Register
鈾?/div>
Interrupt Vector Register
鈾?/div>
Global Chip Configuration Register
鈾?/div>
Watch-dog Timer Run Control
0001 1011 (x1B)
0001 1111 (x1F)
0001 1101 (x1D)
WDTRCR
1998 Sep 21
30

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