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SC28L194 Datasheet

  • SC28L194

  • Quad UART for 3.3V and 5V supply

  • Philips

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Philips Semiconductors
Preliminary specification
Quad UART for 3.3V and 5V supply voltage
SC28L194
GENERAL PURPOSE OUTPUT PIN CONTROL
The following four registers control the function of the Gout0 and
Gout1 pins. These output pins have a unique control matrix which
includes a clocking mechanism that will allow the pin to change
synchronously with an internal or external stimulus. See diagram
below.
Table 41. GPOC- General Purpose Output Clk
Register
This controls the clock source for GPOR that will clock and/or toggle
the data from the selected GPOD source. When code b鈥?0 is
selected, no clock will be provided, thereby preventing any change
through the D port.
Bits 7:6
Bits 5:4
Bits 3:2
Bits 1:0
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Table 39. GPOSR- General Purpose Output
Select Register
GPOSR selects the signal or data source for the Gout pins. The Tx
and Rx clock selection is straight forward. The selection of the
GPOR allows a more flexible timing control of when the Gout pins
change.
Bits 7:4
Bits 3:0
Clk Sel
GPOR(3)
Clk Sel
GPOR(2)
Clk Sel
GPOR(1)
Clk Sel
GPOR(0)
00 = none
01 = GIN0
10 = GIN1
11 = reserved
00 = none
01 = GIN0
10 = GIN1
11 = reserved
00 = none
01 = GIN0
10 = GIN1
11 = I/O3c
00 = none
01 = GIN0
10 = GIN1
11 = I/O3a
Global General Purpose Output
1
Selection
0000 - 0111 reserved
1000 = TxC1x a
1001 = TxC16x a
1010 = RxC16x a
1011 = TxC16x b
1100 = GGPOR(3)
1101 = GGPOR(2)
1110 = GGPOR(1)
1111 = GGPOR(0)
Global General Purpose Output
0
Selection
0000 - 0111 reserved
1000 = TxC1x a
1001 = TxC16x a
1010 = RxC16x a
1011 = TxC16x b
1100 = GGPOR(3)
1101 = GGPOR(2)
1110 = GGPOR(1)
1111 = GGPOR(0)
Table 42. GPOD- General Purpose Output Data
Register
This register selects the data that will be presented to the GPOR 鈥淒鈥?/div>
input. Note that selection b鈥?0 selects the inverted GPOR data as
the input. In this case, the GPOR output will toggle synchronously
with the clock selected in the GPOC.
Bits 7:6
Bits 5:4
Bits 3:2
Bits 1:0
Data Sel
GPOR(3)
Data Sel
GPOR(2)
Data Sel
GPOR(1)
Data Sel
GPOR(0)
Table 40. GPOR- General Purpose Output
Register
00 = 鈥?鈥?/div>
01 = 鈥?鈥?/div>
10 = GPOR3N
11 = reserved
00 = 鈥?鈥?/div>
01 = 鈥?鈥?/div>
10 = GPOR2N
11 = reserved
00 = 鈥?鈥?/div>
01 = 鈥?鈥?/div>
10 = GPOR1N
11 = I/O3d
00 = 鈥?鈥?/div>
01 = 鈥?鈥?/div>
10 = GPOR0N
11 = I/O3b
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Bits 7:4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
GPOR(3)
GPOR(2)
GPOR(1)
GPOR(0)
GPOD
鈥?鈥?/div>
鈥?鈥?/div>
GPORQN
4
This register is a read/write register. Its contents may be altered by a
GPOR Write or by the GPOC and GPOD registers shown below.
The GPOD and GPOC may be programmed to cause the individual
bits of the GPOR to change synchronously with internal or external
events. The cells of this register may be thought of as a 鈥淭wo Port
flip-flop鈥? one port is controlled by a D input and clock, the other by a
data load strobe. A read of the GPOR always returns its current
value regardless of the port from which it was loaded.
GPOR
4:1 MULTIPLEX
DATA BUS 3:0
GPOR R/W
DATA IN/OUT
DATA READ/WRITE
TxC1Xa
TxC16Xa
RxC16Xa
TxC16Xb
GPOSR
GPO PIN
4
D INPUT
GPOR(0)
GPOR(1)
GPOR(2)
GPOR(3)
1/O3b
GPOC
4:1 MULTIPLEX
D CLOCK
NONE
G
IN
0
G
IN
1
1/O3a
4
QN
8:1 MULTIPLEX
SD00526
Figure 3. General Purpose Pin Control Logic
1998 Sep 21
29

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