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SC28L194 Datasheet

  • SC28L194

  • Quad UART for 3.3V and 5V supply

  • 309.02KB

  • Philips

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Philips Semiconductors
Preliminary specification
Quad UART for 3.3V and 5V supply voltage
SC28L194
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Bits 7:0
8 data bits of the Interrupt Vector (IVR)
Bits 7:4
Bits 3:0
The IVR contains the byte that will be placed on the data bus during
an IACKN cycle when the GCCR bits (2:1) are set to binary 鈥?1鈥?
This is the unmodified form of the interrupt vector.
Reserved
Channel byte count code
Table 29. IVR - Interrupt Vector Register
Table 32. GIBCR - Global Interrupting Byte Count
Register
Table 30. Modification of the IVR
Bits 7:5
Bits 4:3
Always contains
bits (7:5) of the IVR
Will be replaced
with current
interrupt type if IVC
field of GCCR = 3
Bits 2:0
0000 = 1 AND RxRDY status set for RxFIFO
0000 = 1 AND TxRDY status set for TxD
0001 = 2
0010 = 3
.
1111 = 16
Replaced with
interrupting channel
number if IVC field of
GCCR > 1
The table above indicates how the IVR may be modified by the
interrupting source. The modification of the IVR as it is presented to
the data bus during an IACK cycle is controlled by the setting of the
bits (2:1) in the GCCR (Global Chip Configuration Register)
A register associated with the interrupting channel as defined in the
CIR. Its numerical value equals the number of bytes minus 1
(count - 1) ready for transfer to the transmitter or transfer from the
receiver. It is undefined for other types of interrupts
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Bits 7:3
Bits 2:0
000 = a
001 = b
010 = c
011 = d
Reserved
Channel code
A register associated with the interrupting channel as defined in the
CIR. It contains the interrupting channel code for all interrupts.
Table 31. GICR - Global Interrupting Channel
Register
Table 33. Global Interrupting Type Register
Bit 7:6
Bit 5
Receiver Interrupt
Transmitter Interrupt
Bit 4:3
Bit 2:0
Reserved
read b鈥?0
Other types
0x - not receiver
10 - with receive errors
11 - w/o receive errors
0 - not transmitter
1 - transmitter interrupt
000 - not 鈥渙ther鈥?type
001 - Change of State
010 - Address Recognition Event
011 - Xon/Xoff status
100 - Not used
101 - Break Change
11x - do not occur
A register associated with the interrupting channel as defined in the
CIR. It contains the type of interrupt code for all interrupts.
1998 Sep 21
27

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