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SC28L194 Datasheet

  • SC28L194

  • Quad UART for 3.3V and 5V supply

  • Philips

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Philips Semiconductors
Preliminary specification
Quad UART for 3.3V and 5V supply voltage
SC28L194
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Bit 7
Bit 6
Bit 5
Bit 4:3
Bit 2
Bit 1:0
RxRTS Control
0 - off
1 - on
ISR Read Mode
Error Mode
Parity Mode
Parity Type
0 = Even
1 = Odd
Bits per Character
00 - 5
01 - 6
10 - 7
11 - 8
0 - ISR unmasked
1 - ISR masked
0 = Character
1 = Block
00 - With Parity
01 - Force parity
10 - No parity
11 - Special Mode
MR1[7]: Receiver Request to Send Control
This bit controls the deactivation of the RTSN output (I/O2) by the
receiver. This output is asserted and negated by commands applied
via the command register. MR1[7] = 1 causes RTSN to be
automatically negated upon receipt of a valid start bit if the receiver
FIFO is 3/4 full or greater. RTSN is reasserted when an the FIFO fill
level falls below 3/4 full. This constitutes a change from previous
members of Philips (Signets)鈥?UART families where the RTSN
function triggered on FIFO full. This behavior caused problems with
PC UARTs that could not stop transmission at the proper time. The
RTSN feature can be used to prevent overrun in the receiver, by
using the RTSN output signal, to control the CTSN input of the
transmitting device.
MR1[6]: Interrupt Status Masking
This bit controls the readout mode of the Interrupt Status Register,
ISR. If set, the ISR reads the current status masked by the IMR, i.e.
only interrupt sources enabled in the IMR can ever show a 鈥?鈥?in the
ISR. If cleared, the ISR shows the current status of the interrupt
source without regard to the Interrupt Mask setting.
MR1[5]: Error Mode Select
This bit selects the operating mode of the three FIFOed status bits
(FE, PE, received break). In the character mode, status is provided
on a character by character basis; the status applies only to the
character at. the bottom of the FIFO. In the block mode, the status
provided in the SR for these bits is the accumulation (logical OR) of
the status for all characters coming to the top of the FIFO, since the
last reset error command was issued.
MR1[4:3]: Parity Mode Select
If 鈥榳ith parity鈥?or 鈥檉orce parity鈥?is selected, a parity bit is added to the
transmitted character and the receiver performs a parity check on
incoming data. MR1[4:3] = 11 selects the channel to operate in the
special Wake-up mode.
MR1[2]: Parity Type Select
This bit sets the parity type (odd or even) if the 鈥檞ith parity鈥?mode is
programmed by MR1[4:3], and the polarity of the forced parity bit if
the 鈥檉orce parity鈥?mode is programmed. It has no effect if the 鈥檔o
parity鈥?mode is programmed. In the special 鈥橶ake-up鈥?mode, it
selects the polarity of the A/D bit. The parity bit is used to an
address or data byte in the 鈥橶ake-up鈥?mode.
MR1[1:0]: Bits per Character Select
This field selects the number of data bits per character to be
transmitted and received. This number does
not
include the start,
parity, or stop bits.
1998 Sep 21
18
Table 4. MR1 - Mode Register 1

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