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SC28L194 Datasheet

  • SC28L194

  • Quad UART for 3.3V and 5V supply

  • Philips

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Philips Semiconductors
Preliminary specification
Quad UART for 3.3V and 5V supply voltage
SC28L194
Table 2. GCCR - Global Configuration Control Register
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Bit 7
Bit 6
Bit 5:3
Bit 2:1
Bit 0
Reserved
Reserved
Sync bus cycles
Reserved
Reserved
Set to 0
IVC, Interrupt Vector Control
Power Down Mode
0 - Device enabled
1 - Power down
Must be set to 0
0 - async cycles
1 - Sync, non-pipe-lined
cycle
00 - no interrupt vector
01 - IVR
10 - IVR + channel code
11 - IVR + interrupt type + channel code
GCCR(7):
This bit is reserved for future versions of this device. If
not set to zero most internal addressing will be disabled!
GCCR(6):
Bus cycle selection
Controls the operation of the host interface logic. If reset, the power
on/reset default, the host interface can accommodate arbitrarily long
bus I/O cycles. If the bit is set, the Quad UART expects four Sclk
cycle bus I/O operations similar to those produced by an i80386
processor in non-pipelined mode. The major differences in these
modes are observed in the DACKN pin function. In Sync mode, no
negation of CEN is required between cycles.
transmission/reception activities cease, and all processing for input
change detection, BRG counter/timers and Address/Xon./Xoff
recognition is disabled.
Note: For maximum power savings it is recommended that all
switching inputs be stopped and all input voltage levels be within 0.5
volt of the Vcc and Vss power supply levels.
To switch from the asynchronous to the synchronous bus cycle
mode, a single write operation to the GCCR, terminated by a
negation of the CEN pin, is required. This cycle may be 4 cycles
long if the setup time of the CEN edge to Sclk can be guaranteed.
The host CPU must ensure that a minimum of two Sclk cycles
elapse before the initiation of the next (synchronous) bus cycle(s).
A hardware or software reset is recommended for the unlikely
requirement of returning to the asynchronous bus cycling mode.
GCCR(2:1):
Interrupt vector configuration
The IVC field controls if and how the assertion of IACKN (the
interrupt acknowledge pin) will form the interrupt vector for the Quad
UART. If b鈥?0, no vector will be presented during an IACKN cycle.
The bus will be driven high (xFF). If the field contains a b鈥?1, the
contents of the IVR, Interrupt Vector Register, will be presented as
the interrupt vector without modification. If IVC = b鈥?0, the channel
code will replace the 3 LSBs of the IVR; if IVC = b鈥?1 then a modified
interrupt type and channel code replace the 5 LSBs of the IVR.
Note: The modified type field IVR(4:3) is:
10
Receiver w/o error
11
Receiver with error
01
Transmitter
00
All remaining sources
GCCR(0):
Power down control
Controls the power down function. During power down the internal
oscillator is disabled, interrupt arbitration and all data
THIS IS A VERY IMPORTANT REGISTER! IT SHOULD BE THE FIRST REGISTER ADDRESSED DURING INITIALIZATION.
This register
has two addresses: x鈥?F and x鈥?F. The Global Configuration Control Register (GCCR) sets the type of bus cycle, interrupt vector modification
and the power-up or -down mode.
MR - Mode Registers
The user must exercise caution when changing the mode of running
receivers, transmitters or BRG counter/timers. The selected mode
will be activated immediately upon selection, even if this occurs
during the reception or transmission of a character. It is also
possible to disrupt internal controllers by changing modes at critical
times, thus rendering later transmission or reception faulty or
impossible. An exception to this policy is switching from auto-echo
or remote loop back modes to normal mode. If the deselection
occurs just after the receiver has sampled the stop bit (in most
cases indicated by the assertion of the channel鈥檚 RxRDY bit) and
the transmitter is enabled, the transmitter will remain in auto-echo
mode until the end of the transmission of the stop bit.
1998 Sep 21
16

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