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SC28L194 Datasheet

  • SC28L194

  • Quad UART for 3.3V and 5V supply

  • Philips

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Philips Semiconductors
Preliminary specification
Quad UART for 3.3V and 5V supply voltage
SC28L194
communication between the transmitter and receiver is entirely
within the UART - it is essentially 鈥渢alking to itself鈥?
The
remote loop back
mode (also used for diagnostic purposes) is
similar to auto echo except that the characters are not sent to the
local CPU, nor is the receiver status updated. The received data is
sent directly to the transmitter where it is sent out on the TxD output.
The received data is not sent to the receive FIFO and hence the
host will not normally be participating in any diagnostics.
associated with address recognition, data handling, receiver enables
and disables. In both modes the meaning of the parity bit is
changed. It is often referred to as the A/D bit or the address/data bit.
It is used to indicate whether the byte presently in the receiver shift
register is an 鈥渁ddress鈥?byte or a 鈥渄ata鈥?byte. 鈥?鈥?usually means
address; 鈥?鈥?data.
Its purpose is to allow several receivers connected to the same data
source to be individually addressed. Of course addressing could be
by group also. Normally the 鈥淢aster鈥?would send an address byte to
all receivers 鈥渓istening鈥?The receiver would then recognize its
address and enable itself receiving the following data stream. Upon
receipt of an address not its own it would then disable itself. As
descried below appropriate status bits are available to describe the
operation.
Enabling the Wake-up mode
This mode is selected by programming bits MR1[4:3] to 鈥?1鈥? The
sub modes are controlled by bits 6, 1, 0 in the MR0 register. Bit 6
controls the loading of the address byte to the RxFIFO and MR0[1:0]
determines the sub mode as shown in the following table.
MR0[1:0] = 00
Normal Wake-up Mode (default). Host controls
operation via interrupts and commands written to
the command register (CR).
Auto wake. Enable receiver on address
recognition for this station. Upon recognition of
its assigned address, in the Auto Wake mode,
the local receiver will be enabled and normal
receiver communications with the host will be
established.
Auto Doze. Disable receiver on address
recognition, not for this station. Upon recognition
of an address character that is not its own, in the
Auto Doze mode, the receiver will be disabled
and the address just received either discarded or
pushed to the RxFIFO depending on the
programming of MR0[6].
Auto wake and doze. Both modes above. The
programming of MR0[1:0] to 11 will enable both
the auto wake and auto doze features.
Minor Modes
The minor modes provide additional features within the major
modes. In general the minor modes provide a reduction in the
control burden and a less stringent interrupt latency time for the host
processor. These modes could be invoked in all of the major
modes.. However it may not be reasonable in many situations.
Watch-dog Timer Time-out Mode
Each receiver in the Quad UART is equipped with a watch-dog timer
that is enabled by the 鈥淲atch-dog Timer Enable Register (WTER).
The watch-dog 鈥渂arks鈥?(times out) if 64 counts of the receiver clock
(64 bit times) elapse with no RxFIFO activity. RxFIFO events are a
read of the RxFIFO or GRxFIFO, or the push of a received character
into the RxFIFO. The timer resets when the (G)RxFIFO is read or if
another character is pushed into the RxFIFO. The receiver
watch-dog timer is included to allow detection of the very last
character(s) of a received message that may be waiting in the
RxFIFO, but are too few in number to successfully initiate an
interrupt. The watch-dog timer is enabled for counting if the
channel鈥檚 bit in the Watch Dog Timer Control Register (WDTCR) is
set. Note: a read of the GRxFIFO will reset the watch-dog timer of
only the channel specified in the current interrupt context. Other
watch-dogs are unaffected.
The watch-dog timer may generate an input to the interrupt arbiter if
IMR[6] is set. The status of the Watch-dog timer can be seen as Bit
6 of the Interrupt Status Register, ISR[6]. When a Watch-dog timer
that is programmed to generate an interrupt times out it enters the
arbitration process. It will then only allow receivers to enter the enter
the arbitration. All other sources are bidding sources are disabled.
The receivers arbitrate only amongst themselves.. The receiver only
interrupt mode of the interrupt arbiter continues until the last
watch-dog timer event has been serviced. While in the receiver only
interrupt mode, the control of the interrupt threshold level is also
disabled. The receivers arbitrate only between themselves. The
threshold value is ignored. The receiver with the most FIFO
positions filled will win the bid. Hence the user need not reduce the
bidding threshold level in the ICR to see the interrupt from a nearly
empty RxFIFO that may have caused the watch-dog time-out.
Note: When any watch-dog times our only the receivers arbitrate.
There is no increase in the probability of receiver being serviced
causing the overrun of another receiver since they will still have
priority based upon received character count.
The interrupt will be cleared automatically upon the push of the next
character received or when the RxFIFO or GRxFIFO is read. The
ICR is unaffected by the watch-dog time-out interrupt and normal
interrupt threshold level sensing resumes after the last watch-dog
timer event has been processed. If other interrupt sources are
active, the IRQN pin may remain low.
Wake-up Mode
The SC28L194 provides two modes of this common asynchronous
鈥減arty line鈥?protocol: the new automatic mode with 3 sub modes and
the default Host operated mode. The automatic mode has several
sub modes (see below). In the full automatic the internal state
machine devoted to this function will handle all operations
MR0[1:0] = 01
MR0[1:0] = 10
MR0[1:0] = 11
The enabling of the wake-up mode executes a partial enabling
of the receiver state machine. Even though the receiver has
been reset the Wake-up mode will over ride the disable and
reset condition.
Normal Wake-up (The default configuration)
In the default configuration for this mode of operation, a 鈥檓aster鈥?/div>
station transmits an address character followed by data characters
for the addressed 鈥檚lave鈥?station. The slave stations, whose
receivers are normally disabled (not reset), examine the received
data stream and interrupts the CPU (by setting RxRDY) only upon
receipt of an address character. The CPU (host) compares the
received address to its station address and enables the receiver if it
wishes to receive the subsequent data characters. Upon receipt of
another address character, the CPU may disable the receiver to
initiate the process again.
A transmitted character consists of a start bit, the programmed
number of data bits, an address/data (A/D) bit, and the programmed
number of stop bits. The polarity of the transmitted A/D bit is
selected by the CPU by programming bit MR1[2]. MR1[2] = 0
transmits a zero in the A/D bit position which identifies the
corresponding data bits as
data.
MR1[2] = 1 transmits a one in the
A/D bit position which identifies the corresponding data bits as an
address.
The CPU should program the mode register prior to
loading the corresponding data bytes into the TxFIFO.
1998 Sep 21
13

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