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SC28L198 Datasheet

  • SC28L198

  • Octal UART for 3.3V and 5V supply

  • Philips

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V
CC
= 3.3 volts
"
10%; T
A
= 鈥?0 to 85擄C; unless otherwise specified
1999 Jan 14
Philips Semiconductors
t
SCLKH
t
SCLKL
Sclk Timing
ts
STRT
t
RXH
t
RXS
Receiver Timing
t
TCS
t
TXD
Transmitter Timing
f
TX4
t
TX
f
RX4
t
RX
Tx
/ Rx Clock Timing, External
t
DD
t
IR
Interrupt Timing
t
PD
t
PH
t
PS
I/O Port Pin Timing
t
RWD
t
DH
t
DS
t
DF
t
DD
t
RWH
t
RWS
t
STP
t
CH
t
CS
t
AH
t
AS
Bus Timing
t
RES1
Reset Timing
SYMBOL
FIGURE
Min high time at Vih (2.0V)
Min low time at Vil (0.8V)
RxD data hold time from RxC high (data)
RxD data setup time to RxC high (data)
TxC output delay from TxD output data
TxD output delay from TxC low
TxC frequency (16 X)
(1 X)
TxC high or low time
RxC frequency (16 X)
(1 X)
RxC high or low time
Interrupt vector valid after C3 rising edge
I/O output valid from:
Write Sclk C4 rising edge (write to I/OPIOR)
High time between CEN low (ASYNC)
W-Rn hold time after Sclk C3 rising edge
W-Rn setup time before Sclk C2 rising edge
CEN hold time after Sclk C4 high (ASYNC)
CEN hold time after Sclk C3 high (SYNC)
A0-A7 hold time after Sclk C3 rising edge
RESET pulse width
PARAMETER
AC ELECTRICAL CHARACTERISTICS FOR COMMERCIAL AND INDUSTRIAL (3.3V)
Octal UART for 3.3V and 5V supply voltage
RxD data low time to for receiving a valid Start Bit
IRQN from:
Internal interrupt source active bid
Software reset to IRQN inactive
Write IMR (set or clear IMR bit))
3
to IRQN inactive
I/O input hold time after Sclk C4 rising edge (Read IPR)
I/O input setup time before Sclk C3 falling edge (Read IPR)
Write cycle data hold time after Sclk C4 rising edge
Write cycle data setup time before Sclk C4 rising edge
Read cycle data bus floating after C4 end (SYNC)
Read cycle data bus floating after CEN high (ASYNC)
Read cycle Data valid after Sclk C3 falling edge
Cen high befoe next C2 to stop next cycle (Sync Mode)
2
CEN setup time before Sclk C2 high (SYNC)
CEN setup time before Sclk C1 high (ASYNC)
A0-A7 setup time before Sclk C3 rising edge
46
MIN
-15
15
15
25
25
20
25
22
12
18
15
25
25
25
30
50
25
30
22
10
0
0
0
0
7
8
8
17
32
1錕?frac12; Sclk
1錕?frac12; Sclk
1錕?frac12; Sclk
LIMITS
錕?frac12;
Sclk
TYP
10
10
14
14
50
20
26
60
40
50
14
14
17
20
12
11
4
7
8
4
4
3
3
3
MAX
8.0
1
15
90
30
43
90
60
80
20
30
40
8
1
SC28L198
Product specification
bit time
UNIT
MHz
MHz
MHz
Sclk
ns
ns
Sclk
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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