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SC28L198 Datasheet

  • SC28L198

  • Octal UART for 3.3V and 5V supply

  • Philips

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V
CC
= 5.0 volts
"
10%; T
A
= 鈥?0 to 85擄C; unless otherwise specified
NOTES:
1. Timing is illustrated and referenced with respect to W鈥揜N and CEN inputs. Internal read and write activities are controlled by the Sclk as it
generates the several 鈥淐鈥?timing as shown in the timing diagrams.
2. The minimum time before the rising edge of the next C2 time to stop the next bus cycle. CEN must return high after midpoint of C4 time and
before the C2 time of the next cycle.
3. Delay is from CEN high in Async mode to IRQN inactive, from end of C4 to IRQN inactive in Sync mode.
4. The minimum frequency values are not tested, but are guaranteed by design.
5. 1MHz specification is for crystal operation.
1999 Jan 14
Philips Semiconductors
GPOtdd
Gout Timing
tgpirtx
I/O Port External Clock
DAKdlys
DAKdlya
DAKdly
DTACK Timing
TC/TO
TC/TLH
FC/T
4
Counter/Timer Baud Rate Clock (External Clock Input)
T/RFx1
X1 L / H
Fx1
5
X1/X2 Communication Crystal Clock
t/
RFsck
F
sclk
t
sclkh
t
sclkl
Sclk Timing
SYMBOL
FIG#
GPO valid after write to GPOR
I/OP falling edge to TxD out 1X mode
RxD setup to I/OP rising edge 1X mode
GPI to Rx/Tx clock out
DACK high from CEN high (Async)
DACK low from Sclk C4 rising edge
Delay C/T clock external to output pin
C/T high and low time
Clock frequency
X1 Rise and Fall time
X1 Low / High time
Sclk rise and fall time (0.8 to 2.0Volts)
Sclk frequency
Min high time at V
IH
(2.0V)
Min low time at V
IL
(0.8V)
X1 clock frequency
AC ELECTRICAL CHARACTERISTICS FOR COMMERCIAL AND INDUSTRIAL (5V) (Continued)
Octal UART for 3.3V and 5V supply voltage
DACK high from C4 end rising edge (Sync)
PARAMETER
44
MIN
0.1
20
15
32
11
11
0
1
LIMITS
3.6864
TYP
100
135
32
32
10
48
11
11
11
2
5
5
SC28L198
Product specification
MAX
8.0
60
50
20
20
18
60
10
33
8
3
UNIT
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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