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V
CC
= 5.0 volts
"
10%; T
A
= 鈥?0 to 85擄C; unless otherwise specified
1999 Jan 14
Philips Semiconductors
ts
STRT
t
RXH
t
RXS
Receiver Timing
ttcs
t
TXD
Transmitter Timing
t
TX
F
TX4
F
RX4
t
RX
Tx/Rx Clock Timing
t
DD
t
IR
Interrupt Timing
t
PD
t
PH
t
PS
I/O Port Pin Timing
t
RWD
t
DH
t
DS
t
DF
t
DD
t
RWH
t
RWS
t
STP
t
CH
t
AH
t
AS
Bus Timing
t
RES1
Reset Timing
t
CS
SYMBOL
FIG #
RxD data hold time from RxC high (data)
RxD data setup time to RxC high (data)
TxC output delay from TxD output data
TxD output delay from TxC low
TxC high or low time
TxC frequency (16 X)
(1 X)
RxC frequency (16 X)
(1 X)
RxC high or low time
IRQN from:
Internal interrupt source active bid
Reset to IRQN inactive
Write IMR (set or clear IMR bit)
3
I/O input hold time after Sclk C4 rising edge
High time between CEN low (Async)
W鈥揜n hold time after Sclk C3 rising edge
CEN hold time after Sclk C4 high (Async)
CEN hold time after Sclk C3 high (Sync)
CEN setup time before Sclk C1 high (Sync)
A0鈥揂7 hold time after Sclk C3 rising edge
RESET pulse width
PARAMETER
AC ELECTRICAL CHARACTERISTICS FOR COMMERCIAL AND INDUSTRIAL (5V)
Octal UART for 3.3V and 5V supply voltage
RxD data low time for receiving a valid Start Bit
IACKN cycle Data valid after Sclk C3 rising edge
I/O output valid from:
Write Sclk C4 rising edge (write to IOPIOR)
I/O input setup time before Sclk C3 rising edge
Write cycle data hold time after Sclk C4 rising edge
Write cycle data setup time before Sclk C4 rising edge
Read cycle data bus floating after C4 end high (Async)
Read cycle data bus floating after CEN high (Sync)
Read cycle Data valid after Sclk C3 rising edge
W鈥揜n setup time before Sclk C2 rising edge
CEN high before next C2 to stop next cycle (Sync Mode)
2
CEN setup time before Sclk C2 high (Async)
A0鈥揂7 setup time before Sclk C3 rising edge
43
17/32
MIN
鈥?5
15
0
0
15
22
12
18
12
15
25
14
18
25
14
18
10
10
20
20
0
0
5
5
5
LIMIT
1錕?frac12;Sclk
1錕?frac12;Sclk
1錕?frac12;Sclk
錕?frac12;
Sclk
TYP
鈥?
32
4
7
8
1
4
8
3
3
8
2
12
26
32
14
10
10
12
6
SC28L198
Product specification
MAX
15
60
16
1
25
43
75
45
50
15
16
25
16
1
Sclk
ns
Mhz
Mhz
Mhz
Mhz
ns
ns
Sclk
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UNIT
bit
time
ns
ns
ns
ns