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SC28L198 Datasheet

  • SC28L198

  • Octal UART for 3.3V and 5V supply

  • Philips

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Philips Semiconductors
Product specification
Octal UART for 3.3V and 5V supply voltage
SC28L198
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Bits 7:6
Bits 5:4
Bits 3:2
Bits 1:0
I/O3 control
I/O2 control
I/O1 control
I/O0 control
00 鈥?GPI/TxC input
01 鈥?I/OPIOR[3] output
10 鈥?TxC16x output
11 鈥?TxC1x output
00 鈥?GPI/RxC input
01 鈥?I/OPIOR[2]/RTSN *
10 鈥?RxC1x output
11 鈥?RxC16x output
00 鈥?GPI input
01 鈥?I/OPIOR[1]/RTSN *
10 鈥?Reserved
11 鈥?RxC1x output
00 鈥?GPI/CTSN input
01 鈥?I/OPIOR[0]output
10 鈥?TxC1x output
11 鈥?TxC16x output
* If I/OPCR(5:4) is programmed as 鈥?1鈥?then the RTSN functionality
is assigned to I/O2, otherwise, this function can be implemented on
I/O1. (This allows for a lower pin count package option)
Table 38. I/OPCR 鈥?I/O Port Configuration Register
Table 40. GPOR 鈥?General Purpose Output
Register
NOTE: To ensure that CTSN, RTSN and an external RxC are
always available, if I/O2 is not selected as the RTSN output, the
RTSN function is automatically provided on I/O1.
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GENERAL PURPOSE OUTPUT PIN CONTROL
The following four registers control the function of the G
OUT
0 pin.
These output pins have a unique control matrix which includes a
clocking mechanism that will allow the pin to change synchronously
with an internal or external stimulus. See diagram below.
Table 39. GPOSR 鈥?General Purpose Output
Select Register
GPOSR selects the signal or data source for the G
OUT
0 pin. The Tx
and Rx clock selection is straight forward. The selection of the
GPOR allows a more flexible timing control of when the G
OUT
0 pin
changes.
Bits 7:4
Bits 3:0
Reserved
Global General Purpose Output 0 Selection
0000 鈥?0111 reserved
1000 = TxC1x a
1001 = TxC16x a
1010 = RxC16x a
1011 = TxC16x b
1100 = GGPOR(3)
1101 = GGPOR(2)
1110 = GGPOR(1)
1111 = GGPOR(0)
1999 Jan 14
30
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Bits 7:4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
GPOR(3)
GPOR(2)
GPOR(1)
GPOR(0)
This register contains 4, 2 bit fields that set the direction and source
for each of the I/O pins associated with the channel. The I/O2
output may be RTSN if MR1[7] is set, or may signal 鈥漞nd of
transmission鈥?if MR2[5] is set.(Please see the descriptions of these
functions under the MR1 and MR2 register descriptions) If this
control bit is cleared, the pin will use the OPR[2] as a source if
I/OPCR[5:4] is b鈥?1. The b鈥?0 combinations are always inputs. This
register resets to x鈥?, effectively configuring all I/O pins as inputs on
power up or reset. Inputs may be used as RxC, TxC inputs or
CTSN and General Purpose Inputs simultaneously. All inputs are
equipped with change detectors that may be used to generate
interrupts or can be polled, as required.
This register is a read/write register. Its contents may be altered by
a GPOR Write or by the GPOC and GPOD registers shown below.
The GPOD and GPOC may be programmed to cause the individual
bits of the GPOR to change synchronously with internal or external
events. The cells of this register may be thought of as a 鈥淭wo Port
flip-flop鈥? one port is controlled by a D input and clock, the other by a
data load strobe. A read of the GPOR always returns its current
value regardless of the port from which it was loaded.
Table 41. GPOC 鈥?General Purpose Output Clk
Register
This controls the clock source for GPOR that will clock and/or toggle
the data from the selected GPOD source. When code b鈥?0 is
selected, no clock will be provided, thereby preventing any change
through the D port.
Bits 7:6
Bits 5:4
Bits 3:2
Bits 1:0
Clk Sel
GPOR(3)
Clk Sel
GPOR(2)
Clk Sel
GPOR(1)
Clk Sel
GPOR(0)
00 = none
01 = G
IN
0
10 = G
IN
1
11 = reserved
00 = none
01 = G
IN
0
10 = G
IN
1
11 = reserved
00 = none
01 = G
IN
0
10 = G
IN
1
11 = I/O3c
00 = none
01 = G
IN
0
10 = G
IN
1
11 = I/O3a
Table 42. GPOD 鈥?General Purpose Output Data
Register
This register selects the data that will be presented to the GPOR 鈥淒鈥?/div>
input. Note that selection b鈥?0 selects the inverted GPOR data as
the input. In this case, the GPOR output will toggle synchronously
with the clock selected in the GPOC.
Bits 7:6
Bits 5:4
Bits 3:2
Bits 1:0
Data Sel
GPOR(3)
Data Sel
GPOR(2)
Data Sel
GPOR(1)
Data Sel
GPOR(0)
00 = 鈥?鈥?/div>
01 = 鈥?鈥?/div>
10 = GPOR3N
11 = reserved
00 = 鈥?鈥?/div>
01 = 鈥?鈥?/div>
10 = GPOR2N
11 = reserved
00 = 鈥?鈥?/div>
01 = 鈥?鈥?/div>
10 = GPOR1N
11 = I/O3d
00 = 鈥?鈥?/div>
01 = 鈥?鈥?/div>
10 = GPOR0N
11 = I/O3b

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