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SC28L198 Datasheet

  • SC28L198

  • Octal UART for 3.3V and 5V supply

  • Philips

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Philips Semiconductors
Product specification
Octal UART for 3.3V and 5V supply voltage
SC28L198
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XISR[3:2] 鈥?/div>
TxD flow Status. This field tracks the transmitter鈥檚 flow
status as follows:
00 鈥?normal. The flow control is under host control.
01 鈥?TxD halt pending. After the current character finishes the
transmitter will stop. The status will then change to b鈥?0.
10 鈥?re鈥揺nabled. The transmitter had been halted and restarted.
It is sending data characters. After a read of the XISR, it will
return to 鈥漬ormal鈥?status.
11 鈥?disabled. The transmitter is flow controlled.
XISR[1:0] 鈥?/div>
TxD character Status. This field allows determination of
the type of character being transmitted. If XISR(1:0) is b鈥?1, the
channel is waiting for a data character to transfer from the TxFIFO.
This condition will only occur for a bit time after an Xon or Xoff
character transmission unless the TxFIFO is empty.
Table 26. BRGTCR 鈥?BRG Timer Control Register (BRGTCR)
Bit 7
Bit 6:4
Bit 3
BRGTCR b, Register control
BRGTCR b, Clock selection
000 鈥?Sclk / 16
001 鈥?Sclk / 32
010 鈥?Sclk/ 64
011 鈥?Sclk / 128
100 鈥?X1
101 鈥?X1 / 2
110 鈥?I/O1b
111 鈥?G
IN
(1)
0 鈥?Resets the timer register and
holds it stopped
1 鈥?Allows the timer register to
run.
Start/Stop control and clock select register for the two BRG
counters. The clock selection is for the input to the counters. It is
that clock divided by the number represented by the BRGTU and
BRGTL the will be used as the 16x clock for the receivers and
transmitters. When the BRG timer Clock is selected for the
1999 Jan 14
27
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Bits 7:6
Bits 5:4
Bits 3:2
Bits 1:0
Received X Character Sta-
tus
00 鈥?none
01 鈥?Xoff received
10 鈥?Xon received
11 鈥?both received
Automatic X Character transmis-
sion status
00 鈥?none
01 鈥?Xon transmitted
10 鈥?Xoff transmitted
11 鈥?Illegal, does not occur
TxD flow status
TxD character status
00 鈥?normal
01 鈥?TxD halt pending
10 鈥?re鈥揺nabled
11 鈥?flow disabled
00 鈥?normal TxD data
01 鈥?wait on normal data
10 鈥?Xoff in pending
11 鈥?Xon in pending
XISR[7:6] 鈥?/div>
Received X Character Status. This field can be read to
determine if the receiver has encountered an Xon or Xoff character
in the incoming data stream. These bits are maintained until a read
of the XISR. The field is updated by X character reception
regardless of the state of MR0(7, 3:2) or IMR(4). The field can
therefore be used as a character detector for the bit patterns stored
in the Xon and Xoff Character Registers.
XISR[5:4] 鈥?/div>
Automatic transmission Status. This field indicates the
last flow control character sent in the Auto Receiver flow control
mode. If Auto Receiver mode has not been enabled, this field will
always read b鈥?0. It will likewise reset to b鈥?0 if MR0(3) is reset. If
the Auto Receiver mode is exited while this field reads b鈥?0, it is the
user鈥檚 responsibility to transmit an Xon, when appropriate.
Table 22. XISR 鈥?Xon鈥揦off Interrupt Status Register
Table 23. WDTRCR 鈥?Watch-dog Timer Enable
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
WDT
h
WDT
g
WDT
f
WDT
e
WDT
d
WDT
c
WDT
b
Bit 0
WDT
a
1 on
1 on
1 on
1 on
1 on
1 on
1 on
1 on
0 off
0 off
0 off
0 off
0 off
0 off
0 off
0 off
This register enables the watch-dog Timer for each of the 8
receivers on the Octal UART.
Table 24. BRGTRU
鈥?/div>
BRG Timer Reload
Registers, Upper
Bits 7:0
8 MSB of the BRG Timer divisor.
This is the upper byte of the 16 bit value used by the BRG timer in
generating a baud rate clock
Table 25. BRGTRL
鈥?/div>
BRG Timer Reload
Registers, Lower
Bits 7:0
8 LSB of the BRG Timer divisor.
This is the lower byte of the 16 bit value used by the BRG timer in
generating a baud rate clock.
Bit 2:0
BRGTCR a, Register control
BRGTCR a, Clock selection
000 鈥?Sclk / 16
001 鈥?Sclk / 32
010 鈥?Sclk / 64
011 鈥?Sclk / 128
100 鈥?X1
101 鈥?X1 / 2
110 鈥?I/O1a
111 鈥?G
IN
(0)
0 鈥?Resets the timer register and
holds it stopped.
1 鈥?Allows the timer register to
run.
receiver(s) or transmitter(s) the receivers and transmitters will
consider it as a 16x clock and further device it by 16. In other words
the receivers and transmitters will always be in the 16x ode of
operation when the internal BRG timer is selected for their clock.

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