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SC28L198 Datasheet

  • SC28L198

  • Octal UART for 3.3V and 5V supply

  • Philips

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Philips Semiconductors
Product specification
Octal UART for 3.3V and 5V supply voltage
SC28L198
10110
10111
11000
mechanism to initialize all the Xoff Character registers to a
default value with one write. Execution of this command
is immediate and does not effect the timing of subsequent
host I/O operations.
Xoff resume command (CRXoffre; not active in
鈥淎uto-Transmit Mode鈥?. A command to cancel a previous
Host Xoff command. Upon receipt, the channel鈥檚
transmitter will transfer a character, if any, from the
TxFIFO and begin transmission.
Host Xoff command (CRXoff). This command allows tight
host CPU control of the flow control of the channel
transmitter. When interrupted for receipt of an Xoff
character by the receiver, the host may stop transmission
of further characters by the channel transmitter by issuing
the Host Xoff command. Any character that has been
transferred to the TxD shift register will complete its
transmission, including the stop bit.
Cancel Host transmit flow control command. Issuing this
command will cancel a previous transmit command if the
flow control character is not yet loaded into the TxD Shift
Register. If there is no character waiting for transmission
or if its transmission has already begun, then this
command has no effect.
11001鈥?1011
Reserved
11011 Reset Address Recognition Status. This command clears the
interrupt status that was set when an address character
was recognized by a disabled receiver operating in the
special mode.
11100鈥?1101
Reserved
11110
Resets all UART channel registers. This command
provides a means to zero all the UART channels that are
not reset to x鈥?0 by a reset command or a hardware reset.
11111
Reserved for channels b-h, for channel a: executes a chip
wide reset. Executing this command in channel a is
equivalent to a hardware reset with the RESETN pin.
Executing in channel b-h, has no effect.
Table 9. Command Register Code
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Channel Command
Code
CR[7:3]
00000
00001
00010
00011
00100
00101
00110
00111
Channel
Command
NOP
Channel Command
Code
CR[7:3]
10000
10001
10010
10011
10100
10101
10110
10111
Channel
Command
Description
Reserved
Description
Transmit Xon
Transmit Xoff
Reset Receiver
Gang Write Xon Character Registers *
Gang Write Xoff Character Registers *
Reset Transmitter
Reset Error Status
Gang Load Xon Character Registers DC1 *
Gang Load Xoff Character Registers DC3 *
Xoff Resume Command
Host Xoff Command
Reserved
Reserved
Reserved
Reserved
Reset Break Change Interrupt
Begin Transmit Break
End Transmit Break
01000
01001
01010
01011
01100
01101
01110
01111
Assert RTSN (I/O2 or I/O1)
Set time鈥搊ut mode on
Reserved
Set time鈥搊ut mode off
Reserved
Reserved
11000
11001
11010
11011
11100
11101
11110
11111
Cancel Transmit X Char command
Negate RTSN (I/O2 or I/O1)
Reset Address Recognition Status
Block Error Status configure
Reset All UART channel registers
Reset Device *
Commands x鈥?2, x13, x鈥?4, x鈥?5, x鈥?f (marked with*) are global and exist only in channel A鈥檚 register space.
Table 10. SR 鈥?Channel Status Register
Bit 7
Bit 6
Bit 5
Received
Break
0 鈥?No
1 鈥?Yes
Framing Error
0 鈥?No
1 鈥?Yes
Parity
Error
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Overrun Error
0 鈥?No
1 鈥?Yes
TxEMT
TxRDY
RxFULL
0 鈥?No
1 鈥?Yes
RxRDY
0 鈥?No
1 鈥?Yes
0 鈥?No
1 鈥?Yes
0 鈥?No
1 鈥?Yes
0 鈥?No
1 鈥?Yes
SR[7] 鈥?Received Break
This bit indicates that an all zero character of the programmed
length has been received without a stop bit. Only a single FIFO
position is occupied when a break is received; further entries to the
FIFO are inhibited until the RxD line returns to the marking state for
at least one half bit time (two successive edges of the internal or
external 1x clock). When this bit is set, the change in break bit in
the ISR (ISR[2]) is set. ISR[2] is also set when the end of the break
condition, as defined above, is detected. The break detect circuitry
is capable of detecting breaks that originate in the middle of a
1999 Jan 14
received character. However, if a break begins in the middle of a
character, it must last until the end of the next character in order for
it to be detected.
SR[6] 鈥?Framing Error (FE)
This bit, when set, indicates that a stop bit was not detected when
the corresponding data character in the FIFO was received. The
stop bit check is made in the middle of the first stop bit position.
SR[5] 鈥?Parity Error (PE)
23

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