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SC28L198 Datasheet

  • SC28L198

  • Octal UART for 3.3V and 5V supply

  • 362.88KB

  • Philips

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Philips Semiconductors
Product specification
Octal UART for 3.3V and 5V supply voltage
SC28L198
asserted (low), the character is transmitted. If it is negated (high),
the TxD output remains in the marking state and the transmission is
delayed until CTSN goes low. Changes in CTSN, while a character
is being transmitted, do not affect the transmission of that character.
This feature can be used to prevent overrun of a remote receiver.
MR2[3:2] 鈥?/div>
RxINT control field
Controls when interrupt arbitration for a receiver begins based on
RxFIFO fill level. This field allows interrupt arbitration to begin when
the RxFIFO is full, 3/4 full, 1/2 full or when it contains at least 1
character.
MR2[1:0] 鈥?/div>
Stop Bit Length Select
This field programs the length of the stop bit appended to the
transmitted character. Stop bit lengths of 9/16, 1, 1.5 and 2 bits can
be programmed for character lengths of 6, 7, and 8 bits. For a
character length of 5 bits, 1, 1.5 and 2 stop bits can be programmed.
In all cases, the receiver only checks for a mark condition at the
center of the first stop bit position (one bit time after the last data bit,
or after the parity bit if parity is enabled). If an external 1X clock is
used for the transmitter, MR2[1] = 0 selects one stop bit and MR2[1]
= 1 selects two stop bits to be transmitted.
Table 6. RxCSR and TxCSR 鈥?Receiver and Transmitter Clock Select Registers
Both registers consist of single 5 bit field that selects the clock source for the receiver and transmitter, respectively. The unused bits in this
register read b鈥?11. The baud rates shown in the table below are based on the x1 crystal frequency of 3.6864MHz. The baud rates shown
below will vary as the X1 crystal clock varies. For example, if the X1 rate is changed to 7.3728 MHz all the rates below will double.
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Bits 7:5
Bits 4:0
Reserved
Transmitter/Receiver Clock select code, (see Clock Mux Table below)
Table 7. Data Clock Mux
Clock Select Code
CSR (4:0)
00000
00001
00010
00011
00100
00101
00110
00111
CCLK maximum rate is 8MHz. Data clock rates will follow exactly the ratio of CCLK to 3.6864MHz.
Clock selection,
CCLK = 3.6864 MHz
BRG 鈥?50
BRG 鈥?75
Clock Select Code
10000
10001
10010
10011
10100
10101
10110
10111
Clock selection,
CCLK = 3.6864 MHz
BRG 鈥?19.2K
BRG 鈥?28.8K
BRG 鈥?38.4K
BRG 鈥?57.6K
BRG 鈥?150
BRG 鈥?200
BRG 鈥?300
BRG 鈥?450
BRG 鈥?600
BRG 鈥?900
BRG 鈥?115.2K
G
IN
0
G
IN
1
BRG 鈥?230.4K
01000
01001
01010
01011
01100
01101
01110
01111
BRG 鈥?1200
BRG 鈥?1800
BRG 鈥?2400
BRG 鈥?3600
BRG 鈥?4800
BRG 鈥?7200
BRG 鈥?9600
11000
11001
11010
11011
11100
11101
11110
11111
BRG C/T 0
BRG C/T 1
Reserved
I/O2 rcvr, I/O3 xmit 鈥?6x
I/O2 rcvr, I/O3 xmit鈥?x
Reserved
Reserved
Reserved
BRG 鈥?14.4K
1999 Jan 14
21

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