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74AHC32 Datasheet

  • 74AHC32

  • Quad 2-input OR gate

  • 81.90KB

  • Philips

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Philips Semiconductors
Product speci鏗乧ation
Quad 2-input OR gate
FEATURES
鈥?/div>
ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V
MM EIA/JESD22-A115-A
exceeds 200 V
CDM EIA/JESD22-C101
exceeds 1000 V
鈥?/div>
Balanced propagation delays
鈥?/div>
All inputs have Schmitt-trigger
actions
鈥?/div>
Inputs accepts voltages higher than
V
CC
鈥?/div>
For AHC only:
operates with CMOS input levels
鈥?/div>
For AHCT only:
operates with TTL input levels
鈥?/div>
Specified from
鈭?0
to +85 and +125
擄C.
DESCRIPTION
The 74AHC/AHCT32 are high-speed
Si-gate CMOS devices and are pin
compatible with low power Schottky
TTL (LSTTL). They are specified in
compliance with JEDEC standard
No. 7A.
The 74AHC/AHCT32 provides the
2-input OR function.
FUNCTION TABLE
See note 1.
INPUT
nA
L
L
H
H
Note
1. H = HIGH voltage level
L = LOW voltage level.
nB
L
H
L
H
OUTPUT
nY
L
H
H
H
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
擄C;
t
r
= t
f
鈮?/div>
3.0 ns.
74AHC32; 74AHCT32
TYPICAL
SYMBOL
t
PHL
/t
PLH
C
I
C
O
C
PD
PARAMETER
propagation delay
nA, nB to nY
input capacitance
output capacitance
power dissipation
capacitance
C
L
= 50 pF;
f = 1 MHz;
notes 1 and 2
CONDITIONS
AHC
C
L
= 15 pF;
V
CC
= 5 V
V
I
= V
CC
or GND
3.5
3.0
4.0
10
AHCT
5.0
3.0
4.0
12
ns
pF
pF
pF
UNIT
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
碌W).
P
D
= C
PD
脳
V
CC2
脳
f
i
+
鈭?/div>
(C
L
脳
V
CC2
脳
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
鈭?/div>
(C
L
脳
V
CC2
脳
f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts.
2. The condition is V
I
= GND to V
CC
.
PINNING
PIN
1, 4, 9 and 12
2, 5, 10 and 13
3, 6, 8 and 11
7
14
SYMBOL
1A to 4A
1B to 4B
1Y to 4Y
GND
V
CC
DESCRIPTION
data inputs
data inputs
data outputs
ground (0 V)
DC supply voltage
1999 Sep 27
2

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