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74LV32 Datasheet

  • 74LV32

  • Quad 2-input OR gate

  • 113.97KB

  • Philips

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Philips Semiconductors
Product specification
Quad 2-input OR gate
74LV32
FEATURES
鈥?/div>
Wide operating voltage: 1.0 to 5.5 V
鈥?/div>
Optimized for Low Voltage applications: 1.0 to 3.6 V
鈥?/div>
Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
鈥?/div>
Typical V
OLP
(output ground bounce) < 0.8 V at V
CC
= 3.3 V,
鈥?/div>
Typical V
OHV
(output V
OH
undershoot) > 2 V at V
CC
= 3.3 V,
鈥?/div>
Output capability: standard
鈥?/div>
I
CC
category: SSI
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25擄C; t
r
= t
f
鈮?/div>
2.5 ns
SYMBOL
t
PHL
/t
PLH
C
I
C
PD
PARAMETER
Propagation delay
nA, nB to nY
Input capacitance
Power dissipation capacitance per gate
T
AMB
= 25擄C.
T
amb
= 25擄C.
DESCRIPTION
The 74LV32 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT32.
The 74LV32 provides the 2-input OR function.
CONDITIONS
C
L
= 15 pF;
V
CC
= 3.3 V
V
I
= GND to V
CC1
TYPICAL
6
3.5
16
UNIT
ns
pF
pF
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
碌W)
P
D
= C
PD
脳
V
CC2
脳
f
i
)
(C
L
脳
V
CC2
脳
f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
(C
L
脳
V
CC2
脳
f
o
) = sum of the outputs.
ORDERING INFORMATION
PACKAGES
14-Pin Plastic DIL
14-Pin Plastic SO
14-Pin Plastic SSOP Type II
14-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
鈥?0擄C to +125擄C
鈥?0擄C to +125擄C
鈥?0擄C to +125擄C
鈥?0擄C to +125擄C
OUTSIDE NORTH AMERICA
74LV32 N
74LV32 D
74LV32 DB
74LV32 PW
NORTH AMERICA
74LV32 N
74LV32 D
74LV32 DB
74LV32PW DH
PKG. DWG. #
SOT27-1
SOT108-1
SOT337-1
SOT402-1
PIN DESCRIPTION
PIN NUMBER
1, 4, 9, 12
2, 5, 10, 13
3, 6, 8, 11
7
14
SYMBOL
1A 鈥?4A
1B 鈥?4B
1Y 鈥?4Y
GND
V
CC
NAME AND FUNCTION
Data inputs
Data inputs
Data Outputs
Ground (0 V)
Positive supply voltage
FUNCTION TABLE
INPUTS
nA
L
L
H
H
H = HIGH voltage level
L = LOW voltage level
nB
L
H
L
H
OUTPUTS
nY
L
H
H
H
1998 Apr 20
2
853-1897 19258

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