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MC68HC812A4 Datasheet

  • MC68HC812A4

  • Microcontrollers

  • Motorola   Motorola

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Resets and Interrupts
Interrupt Recognition
4.7.5 Central Processor Unit
After reset, the CPU fetches a vector from the appropriate address and
begins executing instructions. The stack pointer and other CPU registers
are indeterminate immediately after reset. The CCR X and I interrupt
mask bits are set to mask any interrupt requests. The S bit is also set to
inhibit the STOP instruction.
4.7.6 Memory
After reset, the internal register block is located at $0000鈥?01FF and
RAM is at $0800鈥?0BFF. EEPROM is located at $1000鈥?1FFF in
expanded modes and at $F000鈥?FFFF in single-chip modes.
4.7.7 Other Resources
The timer, serial communications interface (SCI), serial peripheral
interface (SPI), and analog-to-digital converter (ATD) are off after reset.
4.8 Interrupt Recognition
Once enabled, an interrupt request can be recognized at any time after
the I bit in the CCR is cleared. When an interrupt request is recognized,
the CPU responds at the completion of the instruction being executed.
Interrupt latency varies according to the number of cycles required to
complete the instruction. Some of the longer instructions can be
interrupted and resume normally after servicing the interrupt.
When the CPU begins to service an interrupt request, it:
鈥?/div>
鈥?/div>
鈥?/div>
Clears the instruction queue
Calculates the return address
Stacks the return address and the contents of the CPU registers
as shown in
Table 4-2
Advance Information
MOTOROLA
Resets and Interrupts
MC68HC812A4
鈥?/div>
Rev. 3.0
77

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