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MC68HC812A4 Datasheet

  • MC68HC812A4

  • Microcontrollers

  • 3859.31KB

  • Motorola   Motorola

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Central Processor Unit (CPU12)
3.7 Indexed Addressing Modes
The CPU12 indexed modes reduce execution time and eliminate code
size penalties for using the Y index register. CPU12 indexed addressing
uses a postbyte plus zero, one, or two extension bytes after the
instruction opcode.
The postbyte and extensions do these tasks:
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Specify which index register is used
Determine whether a value in an accumulator is used as an offset
Enable automatic pre- or post-increment or decrement
Specify use of 5-bit, 9-bit, or 16-bit signed offsets
Table 3-2. Summary of Indexed Operations
Postbyte Source Code
Code (xb)
Syntax
,r
rr0nnnnn n,r
鈥搉,r
Comments
rr: 00 = X, 01 = Y, 10 = SP, 11 = PC
5-bit constant offset
n = 鈥?6 to +15
r can specify x, y, sp, or pc
Constant offset
(9- or 16-bit signed)
z:0 = 9-bit with sign in LSB of postbyte(s)
1 = 16-bit
if z = s = 1, 16-bit offset indexed-indirect (see below)
rr can specify x, y, sp, or pc
16-bit offset indexed-indirect
rr can specify x, y, sp, or pc
Auto pre-decrement/increment
or
Auto post-decrement/increment;
p = pre-(0) or post-(1), n = 鈥? to 鈥?, +1 to +8
rr can specify x, y, or sp (pc not a valid choice)
Accumulator offset
(unsigned 8-bit or 16-bit)
aa:00 = A
01 = B
10 = D (16-bit)
11 = see accumulator D offset indexed-indirect
rr can specify x, y, sp, or pc
Accumulator D offset indexed-indirect
rr can specify x, y, sp, or pc
111rr0zs
n,r
鈥搉,r
111rr011 [n,r]
n,鈥搑
n,+r
rr1pnnnn
n,r鈥?/div>
n,r+
A,r
111rr1aa B,r
D,r
111rr111 [D,r]
MC68HC812A4
鈥?/div>
Rev. 3.0
66
Central Processor Unit (CPU12)
Advance Information
MOTOROLA

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