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CY7C09269V Datasheet

  • CY7C09269V

  • 3.3V 16K/32K/64K x 16/18Synchronous Dual-Port Static RAM

  • Cypress

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CY7C09269V/79V/89V
CY7C09369V/79V/89V
Switching Waveforms
(continued)
Pipelined Read-to-Write-to-Read (OE = V
IL
)
[19,
26, 27, 28]
t
CH2
CLK
t
CYC2
t
CL2
CE
0
t
SC
CE
1
t
SW
R/W
t
SW
ADDRESS
t
SA
DATA
IN
A
n
t
HA
t
CD2
Q
n
READ
NO OPERATION
WRITE
READ
t
CKHZ
t
HW
A
n+1
A
n+2
A
n+2
t
SD
t
HD
D
n+2
t
CKLZ
t
CD2
Q
n+3
A
n+3
A
n+4
t
HW
t
HC
DATA
OUT
Pipelined Read-to-Write-to-Read (OE Controlled)
[19,
26, 27, 28]
t
CH2
CLK
t
CYC2
t
CL2
CE
0
t
SC
t
HC
CE
1
t
SW
t
HW
R/W
t
SW
A
n
t
HW
A
n+1
t
HA
A
n+2
t
SD
t
HD
D
n+2
t
CD2
D
n+3
t
CKLZ
Q
n
t
OHZ
t
CD2
Q
n+4
A
n+3
A
n+4
A
n+5
ADDRESS
t
SA
DATA
IN
DATA
OUT
OE
READ
WRITE
READ
Notes:
26. Output state (High, LOW, or high impedance) is determined by the previous cycle control signals.
27. CE
0
and ADS = V
IL
; CE
1
, CNTEN, and CNTRST = V
IH
.
28. During 鈥淣o Operation鈥? data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
Document #: 38-06056 Rev. **
Page 10 of 19

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