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TLE6220GP Datasheet

  • TLE6220GP

  • Smart Quad Low-Side Switch

  • Infineon   Infineon

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Data Sheet TLE 6220 GP
Functional Description
The TLE 6220 GP is an quad-low-side power switch which provides a serial peripheral inter-
face (SPI) to control the 4 power DMOS switches, as well as diagnostic feedback. The power
transistors are protected against short to
V
BB
, overload, overtemperature and against over-
voltage by an active zener clamp.
The diagnostic logic recognises a fault condition which can be read out via the serial diagnos-
tic output (SO).
Circuit Description
Power Transistor Protection Functions
9)
Each of the four output stages has its own zener clamp, which causes a voltage limitation at
the power transistor when solenoid loads are switched off. The outputs are provided with a
current limitation set to a minimum of 3 A. The continuous current for each channel is 1A (all
channels ON; depending on cooling).
Each output is protected by embedded protection functions. In the event of an overload or
short to supply, the current is internally limited and the corresponding bit combination is set
(early warning). If this operation leads to an overtemperature condition, a second protection
level (about 170 擄C) will change the output into a low duty cycle PWM (selective thermal shut-
down with restart) to prevent critical chip temperatures.
SPI Signal Description
CS
- Chip Select. The system microcontroller selects the TLE 6220 GP by means of the
CS
pin. Whenever the pin is in a logic low state, data can be transferred from the 碌C and vice
versa.
CS
High to Low transition:
- Diagnostic status information is transferred from the power
outputs into the shift register.
- Serial input data can be clocked in from then on.
- SO changes from high impedance state to logic high or low
state corresponding to the SO bits.
CS
Low to High transition:
- Transfer of SI bits from shift register into output buffers
- Reset of diagnosis register.
To avoid any false clocking the serial clock input pin SCLK should be logic low state during
high to low transition of
CS
. When
CS
is in a logic high state, any signals at the SCLK and SI
pins are ignored and SO is forced into a high impedance state.
9 )
The integrated protection functions prevent an IC destruction under fault conditions and may not be used in normal operation or perma-
nently
.
V1.1
Page
6
26.Aug. 2002

TLE6220GP 產(chǎn)品屬性

  • TLE6220GP

  • 800

  • 集成電路 (IC)

  • PMIC - MOSFET，電橋驅(qū)動(dòng)器 - 內(nèi)部開關(guān)

  • -

  • 低端

  • SPI

  • 4

  • 320 毫歐

  • 3A

  • 6A

  • 4.5 V ~ 5.5 V

  • -40°C ~ 150°C

  • 表面貼裝

  • 20-SOIC（0.433"，11.00mm 寬）裸露焊盤

  • PG-DSO-20

  • 帶卷 (TR)

  • SP000011903SP000308873SP000691118TLE6220GPAUMA2TLE6220GPCUMA1TLE6220GPINTRTLE6220GPNTTLE6220GPTTLE6220GPT-NDTLE6220GPXT

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