鈥?/div>
8 multiplexed input channels (port 6), which can also be used as digital inputs
10-bit resolution
Single or continuous conversion mode
Internal or external start-of-conversion trigger capability
Interrupt request generation after each conversion
Using successive approximation conversion technique via a capacitor array
Built-in hidden calibration of offset and linearity errors
The main functional blocks of the A/D converter are shown in
figure 19.
The A/D converter uses basically two clock signals for operation : the input clock f
IN
(=1/t
IN
) and the
conversion clock f
ADC
(=1/t
ADC
). These clock signals are derived from the C515C system clock
f
OSC
which is applied at the XTAL pins. The input clock f
IN
is equal to f
OSC
. The conversion clock
is limited to a maximum frequency of 2 MHz and therefore must be adapted to f
OSC
by
programming the conversion clock prescaler. The table in
figure 18
shows the prescaler ratios and
the resulting A/D conversion times which must be selected for typical system clock rates.
MCU System Clock ADCL
Rate (f
OSC
)
2 MHz
4 MHz
6 MHz
8 MHz
10 MHz
Figure 18
A/D Converter Clock Selection
0
0
0
0
1
Conversion Clock
f
ADC
[MHz]
.5
1
1.5
2
1.25
Semiconductor Group
43
1997-07-01